Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor
Table 7
Hazard-1.
(a) Type-1: RAW
Dependent register
Instruction
EX.Register
AND,OR, NOT, XOR, ADD, SUB, MUL, MOV
ID.Register. Source
AND, OR, NOT, XOR, ADD, SUB, MUL, MOV
The second type of RAW hazard; for example CMP r1, r0 follow ADD r0, #10, RAW occurred onr0.
(b) Type-2: RAW
Dependent register
Instruction
EX.Register
AND, OR, NOT, XOR, ADD, SUB, MUL, MOV, LDA
ID.Register. Source
CMP
The second type of RAW and WAW hazard; for example, STA m, r0 follow ADD r0, #10, RAW occurred on r0; STA m, r1 follow ADD r0, #10, WAW and occurred on r0.
(c) Type-3: RAW, WAW
Dependent register
Instruction
EX.Register
AND, OR, NOT, XOR, ADD, SUB, MUL, MOV
ID.Register. Source
STA, LDA
(d)
Dependent register
Instruction
EX.Register
LDA
ID.Register. Source
AND, OR, NOT, XOR, ADD, SUB, MUL, MOV
The third type RAW data hazard will occur as the following example ADD r1, r0 follow LDA r0, m occurred on the r0.
(e) Type-4: RAW
Dependent register
Instruction
WB.Register
AND, OR, NOT, XOR, ADD, SUB, MUL, MOV
EX.Register
AND, OR, NOT, XOR, ADD, SUB, MUL, MOV
The third type RAW data hazard will occur as the following example ADD r1, r0 follow SUB r1, r0, RAW occurred on the r0.
