Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

Table 8

Hazard-2.

(a) Type-1: RAW

Dependent register	Instruction
WB.Register	AND, OR, NOT, XOR, ADD, SUB, MUL, MOV
ID.Register.; Source	AND, OR, NOT, XOR, ADD, SUB, MUL, MOV

Ex: ADDr0, #10 →SUBr1, r2 →ANDr3, r0, RAW at r0.

(b) Type-2: RAW

Dependent register	Instruction
WB.Register	AND, OR, NOT, XOR, ADD, SUB, MUL, MOV, LDA
ID.Register.Source	CMP

Ex: ADD r0, #10 →SUBr1, r2 → CMP r3, r0, RAW at r0.

(c) Type-3: RAW, WAR

Dependent register	Instruction
WB.Register	AND, OR, NOT, XOR, ADD, SUB, MUL, MOV
ID.Register.; Source	STA, LDA

Ex: ADD r0, #10 → SUB r1, r2 → STA m[0], r0, RAW at r0.

(d) ADD r0, #10→SUB r1, r2 → STA m[r0], r2, WAW at r0

Dependent register	Instruction
WB.Register	LDA
ID.Register.; Source	AND, OR, NOT, XOR, ADD, SUB, MUL, MOV

Ex: LDA r0, m[10] → SUB r1, r2 → ADD r2, r0, RAW at r0.