A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation

Table 1

The simulation time of the H.264/AVC decoder.

Sequence	Type
	C code	RTL Verilog HDL	Synthesized HDL netlist	SoC prototyping
Stefan	0.02670 Sec.	5 Sec.	4 hrs 5 Min.	0.52328 Sec.
Foreman	0.02452 Sec.	6 Sec.	4 hrs 1 Min.	0.44141 Sec.
Mother-daughter	0.01694 Sec.	6 Sec.	4 hrs 6 Min.	0.31611 Sec.
Average simulation time	0.02272 Sec.	5.6666 Sec.	4 hrs 4 Min.	0.41783 Sec.
Accuracy	Algorithm/untimed	RTL/cycle accurate	Gate level/cycle accurate	Gate level/cycle accurate