Architecture Exploration Based on GA-PSO Optimization, ANN Modeling, and Static Scheduling

Table 2

Configuration of Xtensa-based processors.

Parameter	PBasicConfig	PMultiplier	PMac	PBasicCache	Notes
Xtensa ISA version	LX 2.0	LX 2.0	LX 2.0	LX 2.0
Multiplier units	No	Yes	Yes	No
MAC units	No	No	Yes	No
Pipeline length	5	5	5	7
Instruction/data cache	1024	1024	1024	2048	Bytes
Instruction/data cache line	16	16	16	16	Bytes
Cache associativity	Direct	Direct	Direct	2-way
System RAM	128 K	128 K	128 K	128 K
System ROM	16 K	16 K	16 K	16 K
Process	130 lv	130 lv	130 lv	130 lv
Core max clock speed	300 MHz	300 MHz	300 MHz	300 MHz
Number of gates	44.5 k gates	55 k gates	65 k gates	52.2 k gates	Estimated
Core size (mm^2)	0.45	0.57	0.69	0.54	Estimated
Static power consumption (mW)	0.2763	0.3321	0.3873	0.3061	Simulated
Library name	PBasc	PMult	PMacu	PCach