Architecture Exploration Based on GA-PSO Optimization, ANN Modeling, and Static Scheduling

Table 3

Summary of simulations for Xtensa-based embedded processors.

Benchmark	Mult. operations	Number of simulations	Frequency range	Simulation Time
FIR	40%	99	10 MHz to 200 MHz	10 sec
FFT	17%	72	10 MHz to 200 MHz	10 sec
GR	0%	54	10 MHz to 200 MHz	10 sec