A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

Abstract

A processor design for singular value decomposition (SVD) and compression/decompression of feedback matrices, which are mandatory operations for SVD multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) systems, is proposed and evaluated. SVD-MIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming. An application specific instruction-set processor (ASIP) architecture is adopted to achieve flexibility in terms of operations and matrix size. The proposed processor realizes a high-speed/low-power design and real-time processing by the parallelization of floating-point units (FPUs) and arithmetic instructions specialized in complex matrix operations.

1. Introduction

In recent years, multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) has been attracting attention as a scheme for achieving high-speed and large-capacity wireless communications. MIMO-OFDM has been adopted for the current wireless LAN standard, IEEE 802.11n [1], and for the next-generation wireless LAN standard, IEEE 802.11ac [2].

It is possible to increase the communication capacity in MIMO systems by increasing the number of transmit and receive antennas; however, communication quality is degraded by the consequent multistream interference. As a solution to this degradation problem, singular value decomposition (SVD) MIMO systems are used. In the case of SVD-MIMO systems, it is possible to suppress multistream interference and to improve communication quality with beamforming using SVD [3]. The implementation of SVD by applying custom hardware processors has been reported in recent studies [4–7]. These processors provide high-speed calculation and enough accuracy for 4 × 4 SVD-MIMO systems. However, SVD-MIMO systems require not only SVD calculation but also other operations such as compression and decompression of feedback matrices [8] and should support a variety of matrix sizes depending on their configuration. Additionally, applying dedicated hardware only to SVD calculation is not superior in terms of utilization efficiency. Therefore, we have employed an application specific instruction-set processor (ASIP) architecture to achieve both flexibility and high processing efficiency. The ASIP implementation of QR decomposition supporting MIMO systems has been presented in [9]. However, it does not support SVD-MIMO systems.

This study mainly deals with 4 × 4 SVD-MIMO-OFDM systems; in particular, flexible processor supporting SVD of MIMO channel matrices and compression/decompression of feedback matrices was designed. The processor achieves efficient, real-time processing by parallelization of floating-point units (FPUs) and arithmetic instructions specialized in complex matrix operations. Since the processor employs an ASIP architecture and a floating-point data format, it can deal with other operations and larger matrix sizes (e.g., 8 × 8) while keeping high calculation accuracy. The improvement compared to our previous work [10] has been achieved by simplifying FPUs and optimizing calculation bit length. Additionally, a “packet-skip” method for reducing energy consumption and improving communication throughput is proposed and evaluated.

This paper is organized as follows. The theory of SVD-MIMO systems is explained in Section 2, and the algorithm of SVD and matrix compression/decompression is described in Section 3. Section 4 explains the structure of the proposed processor. Section 5 presents the evaluated performance of the designed circuit. The packet-skip method is explained and evaluated in Section 6. Section 7 presents the conclusions drawn from this study.

2. SVD-MIMO System

In an MIMO system with 𝑁 transmit antennas and receive antennas, a transmission signal, 𝐱∈ℂ^𝑁×1 goes through a propagation, 𝐇∈ℂ^𝑁×𝑁. A received signal, 𝐲∈ℂ^𝑁×1, is expressed as 𝐲=𝐇𝐱+𝐧, (1) where 𝐧∈ℂ^𝑁×1 is white Gaussian noise. A block diagram of an SVD-MIMO-OFDM system is illustrated in Figure 1. An SVD-MIMO system assumes that channel-state information (CSI) is known in a transmitter and a receiver. By SVD, the channel matrix, 𝐇, is decomposed into a diagonal matrix, 𝚺, and two unitary matrices, 𝐔 and 𝐕, as 𝐇=𝐔𝚺𝐕^𝐻. (2) By beamforming using a transmit-weight matrix, 𝐕, the received signal is expressed as 𝐲=𝐇𝐕𝐱+𝐧. (3) In addition, by applying a receive-weight matrix, 𝐔^𝐻, the received signal is finally expressed as 𝐲^′=𝐔^𝐻𝐲=𝚺𝐱+𝐔^𝐻𝐧, (4) where 𝚺 is a diagonal matrix having singular values of 𝐇in the diagonal elements. The receiver can therefore receive the signal without multistream interference.

Figure 1 

SVD-MIMO-OFDM system.

To investigate the effect of SVD-MIMO on improving transmission performance, bit error rates (BERs) of space-division multiplexing (SDM) MIMO without beamforming and of SVD-MIMO are compared by a baseband simulation. A 4 × 4 MIMO-OFDM system was used for this BER comparison. The simulation parameters are listed in Table 1 and the characteristics of SDM-MIMO and SVD-MIMO are compared in Figure 2. The figure shows that the beamforming by SVD-MIMO gains about 3 to 5 dB in carrier to noise ratio (CNR) for BER of 10⁻³.

Table 1 

Simulation parameters.

Figure 2 

Comparison between characteristics of SDM-MIMO and SVD-MIMO.

3. Algorithm

3.1. Singular Value Decomposition

SVD is a method of matrix decomposition in linear algebra. By SVD, channel matrix 𝐇∈ℂ^𝑁×𝑁 is decomposed as 𝐇=𝐔𝚺𝐕^𝐻, (5) where 𝚺 is an 𝑁×𝑁 diagonal matrix, and its diagonal elements are called singular values: 𝚺=diag𝜎₁,𝜎₂,…,𝜎_𝑁. (6)𝐔and 𝐕are 𝑁×𝑁 unitary matrices. The columns of 𝐔and 𝐕 are, respectively, called “left singular vectors” and “right singular vectors.” The SVD of 𝐇=𝐔𝚺𝐕^𝐻 is calculated in the following three steps.(a)Bidiagonalization 𝐇=𝐔₁𝐁𝐕^𝐻₁: calculate upper bidiagonal matrix 𝐁 by bidiagonalization using a Householder transformation.(b)SVD of bidiagonal matrix 𝐁=𝐔₂𝚺𝐕^𝐻₂: execute eigenvalue decomposition of 𝐁^𝐻𝐁=𝐕₂𝚺²𝐕^𝐻₂ by a QR algorithm and calculate 𝐔₂=𝐁𝐕₂𝚺⁻¹ from 𝐕₂, 𝚺.(c)Inverse transform 𝐔=𝐔₁𝐔₂, 𝐕=𝐕₁𝐕₂: calculate unitary matrices 𝐔 and 𝐕 from 𝐔₁ and 𝐔₂ and 𝐕₁ and 𝐕₂, respectively, in steps (a) and (b).

3.1.1. Eigenvalue Decomposition by QR Algorithm

QR is an algorithm for calculating the eigenvalues of a matrix. It executes the QR decomposition iteratively. The QR decomposition decomposes a matrix into a product of a unitary matrix, 𝐐, and an upper triangle matrix, 𝐑. QR is executed by repeating the following operations: 𝐗_𝑘=𝐐_𝑘𝐑_𝑘𝐗_𝑘+1=𝐑_𝑘𝐐_𝑘=𝐐_𝑘⁻¹𝐗_𝑘𝐐_𝑘(𝑘=0,1,…,𝑚). (7) Since this iterative process is a similarity transformation, the eigenvalues of 𝐗₀,…,𝐗_𝑚+1 are all equal. When 𝐗 is a Hermitian matrix, 𝐗_𝑚+1 converges to a diagonal matrix, and the eigenvalues are obtained. When 𝐗_𝑘 is a tridiagonal matrix, 𝐗_𝑘+1 is also a tridiagonal matrix. In the case of SVD calculation, matrix 𝐗=𝐁^𝐻𝐁 is a tridiagonal Hermitian matrix. 𝐗_𝑚+1 therefore converges to diagonal matrix 𝚺²: 𝐗_𝑚+1=𝐐^𝐻_𝑚⋯𝐐^𝐻₀𝐗𝐐₀⋯𝐐_𝑚=𝐐₀⋯𝐐_𝑚^𝐻𝐗𝐐₀⋯𝐐_𝑚=𝐕^𝐻₂𝐁^𝐻𝐁𝐕₂≈𝚺². (8) The Givens rotation algorithm (which is the linear transformation by the matrix for the QR decomposition) is adopted, and the number of iterations in the QR algorithm is set to 10.

3.2. Feedback-Matrix Compression

A SVD-MIMO system has a drawback of which throughput is decreased by “matrix feedback.” To address this drawback, compression of the feedback matrix is effective. Accordingly, the compression method of a unitary matrix that is adopted in the IEEE 802.11n standard [1] is used. This method transforms a unitary matrix into angles by real transformation and the Givens rotation. It assumes that the 𝑁th row of an 𝑁×𝑁 unitary matrix, 𝐕, is transformed into real numbers in the preprocessing. For 𝐕₁=𝐕,    𝑖=1, a matrix, 𝐃_𝑖, which transforms the 𝑖th column into real numbers is generated by 𝐃_𝑖=𝐈_𝑖−1𝟎𝑒^{𝑗𝜙𝑖,𝑖}⋱𝑒^{𝑗𝜙𝑁−1,𝑖}𝟎1, (9) where 𝜙_𝑖,𝑗 is an argument of 𝐕_𝑖 at the 𝑖th row and 𝑗th column. By multiplying 𝐕_𝑖 by 𝐃^∗_𝑖, the 𝑖th column of 𝐕_𝑖 becomes real numbers. As a result, nondiagonal elements at the 𝑖th column in 𝐕^′_𝑖=𝐃^∗_𝑖𝐕_𝑖 become zero according to the Givens rotation. The Givens rotation matrix, 𝐆_𝑖𝑗, and its elements are generated by 𝐆_𝑖𝑗=1⋯0⋯0⋯0⋮⋱⋮⋮⋱⋮0⋯cos𝜓_𝑖𝑗⋯sin𝜓_𝑖𝑗⋯0⋮⋮⋱⋮⋮0⋯−sin𝜓_𝑖𝑗⋯cos𝜓_𝑖𝑗⋯0⋮⋱⋮⋮⋱⋮0⋯0⋯0⋯1,cos𝜓_𝑖𝑗=𝑣^′_𝑗𝑗𝑣^′_𝑖𝑗²+𝑣^′_𝑗𝑗²,sin𝜓_𝑖𝑗=𝑣^′_𝑖𝑗𝑣^′_𝑖𝑗²+𝑣^′_𝑗𝑗². (10)(11)(12) By multiplying 𝐕^′_𝑖 and the Givens rotation matrices 𝐆_𝑖+1,𝑖,𝐆_𝑖+2,𝑖,…,𝐆_𝑁,𝑖, nondiagonal elements at the 𝑖th column in 𝐕^′_𝑖 become zero. Since 𝐕 is a unitary matrix, nondiagonal elements at the 𝑖th row in 𝐕^′_𝑖 also become zero, and the element at the 𝑖th row and the 𝑖th column in 𝐕^′_𝑖 becomes one, which is expressed as 𝐆_𝑁,𝑖⋯𝐆_𝑖+2,𝑖𝐆_𝑖+1,𝑖𝐕^′_𝑖=𝐈_𝑖𝟎𝟎𝐕_𝑖+1. (13) By repeating these processes for 𝑖=2,3,…,𝑁−1, matrix 𝐕 is finally transformed into an identity matrix, 𝐈_𝑁. Here, applying (9) and (10) generates the real transformation matrix, 𝐃, and the Givens rotation matrix, 𝐆, from phases 𝜙 and 𝜓, respectively. Moreover, applying (13) makes it possible to compute 𝐕_𝑖 from 𝐕_𝑖+1 as follows: 𝐕_𝑖=𝐃_𝑖𝐆^𝑇_𝑖+1,𝑖𝐆^𝑇_𝑖+2,𝑖⋯𝐆^𝑇_𝑁,𝑖𝐈_𝑖𝟎𝟎𝐕_𝑖+1. (14) Since the receiver feeds back only phases 𝜙 and 𝜓, the feedback data is transformed from 𝑁² complex elements into 𝑁(𝑁−1) positive real phases. Table 2 compares the feedback data sizes between noncompressed data and compressed data. Each quantization bit rate is determined by a baseband simulation to avoid degradation of communication performance. In the case of noncompressed data, both the real part and the imaginary part are quantized in seven bits. On the other hand, in the case of compressed data, 𝜙 and 𝜓 are quantized in seven bits and five bits, respectively.

Table 2 

Comparison of feedback data sizes.

4. Processor Structure

An application specific instruction-set processor (ASIP) architecture has been employed for the processor architecture, and efficient processing and flexibility were achieved by preparing arithmetic instructions specialized in complex matrix operations.

4.1. Circuit Structure

The circuit structure of the proposed processor is illustrated in Figure 3. Data and instructions are stored to each memory unit, and the processing unit executes instructions in order. The floating-point data format supports complex values, and each part of a complex value consists of a 1-bit sign part, a 𝑊_𝑒-bits exponent part, and 𝑊_𝑚-bits mantissa part, whose format is shown in Figure 4. Basically, each bit length is based on the IEEE 754 standard (𝑊_𝑒=8,𝑊_𝑚=23). Data memories and processing units are arrayed by the number of parallel processing. Two types of data transfers, which are shown in Figure 5, are supported. A single-data transfer sends data to the processing unit one by one. On the other hand, a block-data transfer sends data blocks containing multiple entries to the processing unit. The structure of the processing unit, which consists of nine floating-point units (FPUs) and dedicated circuits for division and square-root operation [11], is shown in Figure 6. “FPU1” to “FPU4” are used for multiplication, and “FPU5” to “FPU9” are used for addition and subtraction; in particular, “FPU9” is used for only CORDIC operations, which are described in Section 4.4. A variety of instructions can be executed by changing the data paths in the processing unit.

Figure 3 

Circuit structure.

Figure 4 

Floating-point data format.

(a)   Single data transfer

(b) Block data transfer

Figure 5 

Types of data transfer.

Figure 6 

Structure of processing unit.

4.2. Instruction Format

The instruction format consists of memory addresses of input data 𝐴, 𝐵, output data 𝐶, and operation type, whose format is shown in Figure 7. The bit lengths are given as log₂𝑁_DW bits and log₂𝑁_OP bits, where 𝑁_DW is the number of data memory words, and 𝑁_OP is the number of instructions. Table 3 lists the instructions supported by the proposed processor.

Table 3 

Instructions.

Figure 7 

Instruction format.

4.3. Complex Operation

The proposed processor achieves efficient processing in complex matrix operations by adopting specialized instructions and an operation-unit structure. For instance, the complex multiplication of 𝐴×𝐵=(𝐴_𝑟+𝑗𝐴_𝑖)(𝐵_𝑟+𝑗𝐵_𝑖)=(𝐴_𝑟𝐵_𝑟−𝐴_𝑖𝐵_𝑖)+𝑗(𝐴_𝑟𝐵_𝑖+𝐴_𝑖𝐵_𝑟)=𝐶_𝑟+𝑗𝐶_𝑖=𝐶 is executed in seven cycles using “FPU1” to “FPU4,” “FPU5,” and “FPU6” for multiplication, subtraction and addition, respectively, as shown in Figure 8. Moreover, the accumulative complex multiplication is executed in nine cycles using the registers of “Accr”, “Acci,” and “FPU7,” and “FPU8” as shown in Figure 9.

Figure 8 

Complex multiplication in the processing unit.

Figure 9 

Accumulative complex multiplication in the processing unit.

4.4. CORDIC Method

The proposed processor executes approximate calculation by the CORDIC (coordinate rotation digital computer) method for calculating trigonometric functions, which is necessary for the matrix compression and decompression. The recurrence formulas used in the CORDIC method are expressed by 𝑋_𝑗+1=𝑋_𝑗−𝑞_𝑗⋅2^−𝑗⋅𝑌_𝑗𝑌_𝑗+1=𝑌_𝑗−𝑞_𝑗⋅2^−𝑗⋅𝑋_𝑗𝑍_𝑗+1=𝑍_𝑗−𝑞_𝑗⋅arctan2^−𝑗,𝑗=0,1,…,𝑛−1. (15) By setting the initial values to 𝑋₀=1∏^𝑛−1_𝑗=01+2^−2𝑗,𝑌₀=0,𝑍₀=𝜃, (16) and selecting −1 or 1 for 𝑞_𝑗 so that 𝑍_𝑗+1 approaches zero, it is possible to calculate cosine and sine values as 𝑋_𝑛≈cos𝜃,𝑌_𝑛≈sin𝜃. (17) On the other hand, setting the initial values to 𝑋₀=1,𝑌₀=𝑌,𝑍₀=0, (18) and selecting −1 or 1 for 𝑞_𝑗 so that 𝑌_𝑗+1 approaches zero makes it possible to calculate an arctangent value as 𝑍_𝑛≈arctan𝑌. (19) To execute the CORDIC operations in the processing unit, five FPUs are used, as shown in Figure 10, where the signs of input data 2^−𝑗, arctan2^−𝑗 at “FPU1,” “FPU2,” and “FPU9” are reversed depending on the condition. The values of 2^−𝑗,arctan2^−𝑗(𝑗=0,1,…,𝑛−1) are loaded from the data memory unit. And the number of iterations used with the CORDIC method is set to 10.

Figure 10 

CORDIC operation in the processing unit.

4.5. Division and Square-Root Operation

In the case that only “FPU1” to “FPU8” are used, the division and square-root operations are executed by approximate calculation using the Newton-Raphson method. However, they require 115 cycles and 1430 cycles, respectively. The implementation of dedicated circuits for division and square-root operation is effective for hardware acceleration. Division and square-root floating-point units [11] were therefore adopted. Since those units can execute division and square-root operation in 11 cycles, calculation time can be significantly reduced.

4.6. Bit-Length Optimization

Since required precision depends on systems, circuit area and power consumption can be reduced by decreasing bit length. To optimize the mantissa bit length of the proposed processor for SVD and matrix compression/decompression, BER characteristics for several bit lengths were evaluated by simulation. The simulation parameters are the same as listed in Table 1, and the characteristics evaluation is shown in Figure 11. From this figure, the optimal mantissa bit length is taken as 12 bits.

Figure 11 

BER evaluation for several mantissa bit lengths

5. Performance Evaluation

5.1. Circuit Design

The proposed processor was designed by using Verilog hardware description language and synthesized in the controller and the processing units by using a 90 nm CMOS standard cell library. The clock frequency was set to 400 MHz (2.5 ns in a clock period), and the supply voltage was set to 1.0 V.

5.2. Circuit Performance

The circuit performance was evaluated in cases with or without division and square-root units. The results are listed in Tables 4 and 5, respectively. The calculation time for all channel matrices of 108 data subcarriers was measured. The number of entries in the block data transfer was set to 18 to minimize energy consumption. According to these results, the implementation of the division and square-root units increases circuit area two-fold and power consumption by half. However, since the calculation time can be reduced to 1/7∼1/9, energy consumption can be reduced to 1/4∼1/6. This comparison shows that the implementation of division and square-root units is effective.

Table 4 

Circuit performance with division and square-root units.

Table 5 

Circuit performance without division and square-root units.

5.3. Bit-Length Limitation

In the previous section, circuit performance without bit length limitation (𝑊_𝑚=23) was evaluated. In contrast, in this section, circuit performance with bit length limitation (𝑊_𝑚=12) is evaluated (see Table 6). In this evaluation, division and square-root units were implemented and the bit-length limitation is applied in multipliers only, which account for large portion of the operation. This result shows that the bit-length limitation can reduce circuit area, power consumption, and energy consumption by about 10%, 20%, and 20%, respectively.

Table 6 

Circuit performance with bit length limitation.

5.4. Processing Time

A timing chart of the SVD-MIMO-OFDM system is shown in Figure 12. It is assumed that the update and feedback of CSI are executed at every packet. The calculation of SVD and the matrix compression must be completed between receiving the preamble of the data packet and sending the feedback-matrix data. When the number of OFDM data symbols, 𝑁_SYM, is 50, the acceptable calculation time is 252 𝜇s. When the proposed processor arrays six processing units by parallel processing, it takes 193 𝜇s for SVD and matrix compression. Since the calculation time is less than the acceptable calculation time, the processor realizes real-time processing.

Figure 12 

Timing chart of SVD-MIMO-OFDM system.

5.5. Comparison with Related Works

The proposed processor is compared here with our previous work [10] and other related works [4–6] in Table 7. Compared with our previous work, the proposed processor has improved throughput by almost four times, even though it also performs matrix compression. This improvement was achieved by simplifying FPUs and imposing the bit-length limitation. In consideration of SVD operation only, the performance of the proposed processor is not superior to that of either [5] or [6]. However, it can realize sufficient real-time processing and support not only SVD but also matrix compression and decompression (MCD). It therefore achieves faster communication throughput than the other processors. Furthermore, since the proposed processor employs an ASIP architecture and floating-point data format, it can deal with other operations and larger matrix sizes while keeping high calculation accuracy. Given these advantage features, it is concluded that the proposed processor can realize an SVD-MIMO-OFDM system more effectively than the other processors.

Table 7 

Performance comparison.

6. Packet-Skip Method

As explained in the previous sections, it was assumed that the system feeds back the weight matrix at every packet. However, if the channel state is changed gradually, it is possible to skip the SVD calculation and the feedback of the weight matrix and to apply the previous weight matrix without degradation of BER. On the basis of this idea, energy consumption can be reduced and communication throughput can be increased by skipping the SVD calculation and the weight-matrix feedback.

6.1. Simulation

To determine the optimal skip number, BER characteristics for several numbers of packet skips were evaluated by simulation. The simulation assumed a communication environment with the 10 Hz Doppler frequency. The simulation parameters are listed in Table 8, and the BER evaluation result is shown in Figure 13. The delay in this figure means the numbers of packet skips. The packet skip is applied from the packet at which the SVD calculation process starts to the packet to which weight matrices are applied. According to this figure, a delay of less than 5 packets is acceptable under this communication environment. Additionally, BER characteristics in a communication environment with the 1 Hz Doppler frequency were evaluated. The simulation parameters are listed in Table 9, and the BER evaluation result is shown in Figure 14. According to this figure, a delay within 30 to 40 packets is acceptable under this communication environment.

Table 8 

Simulation parameters.

Table 9 

Simulation parameters.

Figure 13 

BER evaluation.

Figure 14 

BER evaluation with 1-Hz Doppler frequency

6.2. Skip Method

For packet skipping, two methods (illustrated schematically in Figure 15) are proposed. As for the first method, that is, method A, SVD calculation is executed over one packet and the weight matrices are applied to the next (𝑛+1) packets. The delay produced by method A is (𝑛+1) packets. On the other hand, as for the second method, that is, method B, SVD is calculated over 𝑛 packets, and the weight matrices are applied to the 𝑛 packets after the SVD calculation. The delay produced by method B is (2𝑛−1) packets. In the case of method A, total energy consumption is reduced by 1/(𝑛+1). In the case of method B, the power consumption can be reduced since the calculation time of SVD is longer than that of the nonskip system or method A.

Figure 15 

Packet-skip methods.

6.3. Performance Evaluation

Circuit performance and communication throughput when these skip methods were applied was evaluated. In the evaluation, it was assumed that the delay is 5 packets for a communication environment with the 10 Hz Doppler frequency. Accordingly, 𝑛=4 and 3 for methods A and B, respectively. The results of the performance evaluation are listed in Table 10. In the evaluation, communication throughput was calculated under the assumption that signals are transmitted by 4 × 4 SVD-MIMO (64QAM, 𝑅=3/4, and 50 symbols) and the feedbacks are transmitted by 4 × 4 SDM-MIMO (16QAM, 𝑅=3/4). According to these performance results, method A is the most effective in terms of energy consumption and communication throughput.

Table 10 

Performance evaluation.

7. Concluding Remarks

A processor design for SVD-MIMO-OFDM systems was proposed. The proposed processor employs an ASIP architecture and achieves both flexibility and high throughput by parallelization of FPUs and arithmetic instructions that are specialized in complex matrix operations. In addition, two types of packet-skip method for reducing energy consumption and increasing communication throughput were proposed. In future work, we will deal with larger-scale SVD-MIMO-OFDM systems (e.g., 8 × 8 SVD-MIMO).