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VLSI Design
Volume 2013 (2013), Article ID 643293, 7 pages
http://dx.doi.org/10.1155/2013/643293
Research Article

A High-Efficiency Monolithic DC-DC PFM Boost Converter with Parallel Power MOS Technique

1Department of Electrical Engineering, National Formosa University, No. 64, Wunhua Rd., Huwei Township, Yunlin 632, Taiwan
2Department of Electrical Engineering, National Chung Hsing University, No. 250, Kuo Kuang Rd., Taichung 402, Taiwan
3Department of Electronic Engineering, National Chin-Yi University of Technology, No. 57, Sec. 2, Zhongshan Rd., Taiping Dist., Taichung 411, Taiwan

Received 26 December 2012; Accepted 12 April 2013

Academic Editor: Yeong-Kang Lai

Copyright © 2013 Hou-Ming Chen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper presents a high-efficiency monolithic dc-dc PFM boost converter designed with a standard TSMC 3.3/5V 0.35 μm CMOS technology. The proposed boost converter combines the parallel power MOS technique with pulse-frequency modulation (PFM) technique to achieve high efficiency over a wide load current range, extending battery life and reducing the cost for the portable systems. The proposed parallel power MOS controller and load current detector exactly determine the size of power MOS to increase power conversion efficiency in different loads. Postlayout simulation results of the designed circuit show that the power conversion is 74.9–90.7% efficiency over a load range from 1 mA to 420 mA with 1.5 V supply. Moreover, the proposed boost converter has a smaller area and lower cost than those of the existing boost converter circuits.