Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

<table>(a) IQSERL <svg height="10.8625" id="M38" style="vertical-align:-0.0pt" version="1.1" viewbox="0 0 33.974998 10.8625" width="33.974998" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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</svg> bit array multiplier circuit, (b) transient response.</table>

VLSI Design

fig8

Figure 8

Figure 8: Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic 