Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

<table>Simulation results of the performance comparison of <svg height="10.8625" id="M40" style="vertical-align:-0.0pt" version="1.1" viewbox="0 0 33.974998 10.8625" width="33.974998" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,10.8)"><path d="M456 178h-96v-72q0 -51 12.5 -62.5t72.5 -16.5v-27h-256v27q65 5 78 17t13 62v72h-260v28q182 271 300 426h40v-407h96v-47zM280 225v295h-2q-107 -148 -196 -295h198z" id="x34"></path></g><g transform="matrix(.017,-0,0,-.017,11.996,10.8)"><path d="M528 54l-36 -38l-198 201l-198 -201l-36 38l197 200l-197 201l36 38l198 -202l198 202l36 -38l-197 -201z" id="xD7"></path></g><g transform="matrix(.017,-0,0,-.017,25.748,10.8)"><path d="M456 178h-96v-72q0 -51 12.5 -62.5t72.5 -16.5v-27h-256v27q65 5 78 17t13 62v72h-260v28q182 271 300 426h40v-407h96v-47zM280 225v295h-2q-107 -148 -196 -295h198z" id="x34"></path></g>
</svg> bit array multipliers with frequency.</table>

VLSI Design

fig9

Figure 9

Figure 9: Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic 