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Volume 2013 (2013), Article ID 785281, 12 pages
A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures
Department of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome, Via Eudossiana 18, 00184 Rome, Italy
Received 12 September 2012; Revised 2 December 2012; Accepted 5 December 2012
Academic Editor: Meng-Hsueh Chiang
Copyright © 2013 Mauro Olivieri and Antonio Mastrandrea. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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