A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Table 1

Delay estimates for different adder schemes, assuming 𝑁 bits operands and 𝑚 bits blocks. “Total delay” refers to the worst-case completion time.

	𝑁	𝑚	4	5	6	7	8	9	10	11	12
CSA	32	Total delay	31.7	29.3	28.1	27.4	27.2	28.0	29.1	29.4	30.8
		𝛿SETUP	3.7	3.6	3.5	3.4	3.4	3.3	3.2	3.2	3.2
		𝛿BLOCK	9.2	11.0	12.8	14.7	16.5	18.2	19.8	21.6	23.4
		𝛿MUX	2.7	2.6	2.6	2.5	2.4	2.4	2.4	2.4	2.4
	64	Total delay	57.8	50.6	46.1	43.6	41.2	41.2	40.2	39.8	40.5
		𝛿SETUP	4.0	4.0	3.9	3.8	3.7	3.6	3.6	3.5	3.4
		𝛿BLOCK	10.1	12.4	14.5	16.4	18.5	12.1	21.9	23.8	25.4
		𝛿MUX	3.0	2.9	2.8	2.7	2.7	2.6	2.6	2.6	2.5
CLA/CSA	32	Total delay	29.3	26.0	23.9	22.6	21.8	22.0	22.5	22.8	23.8
		𝛿SETUP	4.2	4.1	4.1	4.2	4.3	4.2	4.0	4.2	4.1
		𝛿BLOCK	4.2	5.0	5.9	7.0	8.3	9.5	10.9	12.6	14.3
		𝛿MUX	3.0	3.0	3.0	3.0	3.1	3.0	2.9	3.0	3.0
	64	Total delay	56.7	49.0	44.1	41.0	38.2	37.5	36.7	36.4	36.7
		𝛿SETUP	4.4	4.5	4.6	4.6	4.8	4.7	4.8	5.0	4.8
		𝛿BLOCK	4.4	5.2	6.2	7.3	8.6	9.9	11.4	13.1	14.8
		𝛿MUX	3.2	3.2	3.3	3.2	3.4	3.4	3.4	3.5	3.4