Research Article

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Table 3

Truth table for the prediction unit of a 32-bit, 4-bit clock, CLA/CSA ECPA for a cycle time equivalent to 25.5 FO4 delay units.

Predicted Binary output

0ā€”00 0
1010 1
ā€”121 0