A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Table 4

Statistical performance data (average speedup with respect to fixed latency implementation).

Design	Random operands	Real operands
[1]	n.a.	1.79
[9]	1.19	1.01
[13]	n.a.	1.78
This work	2.13	2.43