LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

Table 3

Comparison of three proposed full-parallel decoders with the proposed low power Methods 1, 2, and 3 implemented in 65 nm, 1.3 V CMOS, for a (6,32) (2048,1723) LDPC code. Maximum number of iterations is 𝐼_max=15. Power numbers are for 𝐿𝑜𝑤_𝑃𝑜𝑤𝑒𝑟_𝐼𝑡𝑒𝑟𝑎𝑡𝑖𝑜𝑛=6. Normal Mode: Method 1 with 𝐿𝑜𝑤_𝑃𝑜𝑤𝑒𝑟_𝐼𝑡𝑒𝑟𝑎𝑡𝑖𝑜𝑛=0.

	Normal mode	Method 1	Method 2	Method 3
Final area utilization	95%	95%	96%	96%
Core area (mm^2)	5.27	5.27	5.10	5.20
Maximum clock frequency (MHz)	178	178	185	182
Average Power @ Worst case freq (mW)	1396	1215	1172	1196
Throughput @ 𝐼max (Gbps)	24.3	24.3	25.25	24.8
Energy per bit @ 𝐼max (pJ/bit)	57	50	46	48