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Volume 2013 (2013), Article ID 967370, 9 pages
Architecture and Implementation of Fading Compensation for Dynamic Spectrum Access Wireless Communication Systems
Department of Information Systems Engineering, Osaka University, 1-5 Yamada-oka, Suita, Osaka 565-0871, Japan
Received 2 November 2012; Revised 16 May 2013; Accepted 17 May 2013
Academic Editor: Chien-In Henry Chen
Copyright © 2013 Masahide Hatanaka et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
This paper proposes an efficient architecture and implementation of fading compensation dedicated to dynamic spectrum access (DSA) wireless communication. Since pilot subcarrier arrangements are adaptively determined in wireless communication systems with DSA, the proposed architecture employs piecewise linear interpolation to the channel response estimation for data subcarriers in order to increase the channel estimation accuracy. The fading compensation for an orthogonal frequency-division multiplexing (OFDM) symbol is performed within the time for one OFDM symbol to make increase of latency smaller. The proposed architecture guarantees real-time processing with 76 MHz or higher clock frequency. The FPGA implementation of the proposed architecture occupies 1,577 slices and works up to 121 MHz.
In ambient information society, the ICT infrastructure interacts with each person in order to make the one’s surrounding space more comfortable. In this kind of interaction, various types of information are exchanged, ranging from small size such as the control data of air conditioners and room lights to large size of data like video streaming.
Here, wireless mesh networks that use unlicensed radio frequency bands have been the focus of attention as one of the ambient networks. Among various wireless mesh networks, IEEE 802.11 WLAN series and ZigBee using carrier sense multiple access with collision avoidance (CSMA/CA) are expected to achieve popularity due to their capabilities to interconnect. However the following problem arises by using the technique of CSMA/CA. Let us assume that there are two nodes, and , that use IEEE 802.11g  for the former and ZigBee  for the latter, and the radio resource that has requested partially overlaps with that of . In this situation, even if the node uses far fewer radio resources than node requests, the node judges that the band are not available in case the node performs transmission and does not start to transmit data despite the presence of many unused radio resources. This causes the degradation of total transmission performance of the heterogeneous wireless infrastructure.
In order to solve this problem, the so-called cognitive radio systems have been proposed [3, 4], which introduce various techniques with dynamic spectrum access (DSA). These techniques are based on the concept of exploiting spatial and temporal spectrum white space. Among them,  proposed dynamic subcarrier selection technique based on CSMA/CA with orthogonal frequency division multiplexing (OFDM). In this technique, wireless nodes select the radio resources being used in the units of subcarriers by referring to the result of subcarrier level carrier sensing as shown in Figure 1. This adaptive subcarrier selection technique enables transmission by utilizing unused subcarriers even if there are occupied spectrum components for other transmissions.
Generally in wireless communication, received signals are distorted by fading and noise. Therefore, receivers need to compensate the distortion in order to decode data correctly. If the wireless communication is based on OFDM, known training signals called pilots are utilized in order to estimate the channel response and compensate the distortion . In the IEEE 802.11g, four of the fixed subcarriers are utilized for pilot signals, and the channel responses of data subcarriers are estimated by interpolating the channel responses of pilot subcarriers .
However it is decided adaptively which subcarriers are utilized as data subcarriers or pilot subcarriers in target wireless communication with DSA . Figure 2 outlines the arrangements of pilot subcarriers for IEEE 802.11g and DSA . Although increasing the number of pilot subcarriers enables channel responses to be accurately estimated, it also degrades the data rate. Therefore, it is necessary to estimate the channel responses for data subcarriers by interpolation with the estimated channel responses for pilot subcarriers in order to accurately estimate the channel responses with limited pilot subcarriers. Since the interpolation function for communication differs from the functions for other communications, a dedicated channel compensation circuit for DSA is necessary to accomplish high-speed operation to determine both decisions of interpolation function and fading compensation.
Motivated by these tendencies, this paper describes an efficient architecture and implementation of fading compensator for an OFDM baseband transceiver with DSA. Piecewise linear interpolation is utilized in order to estimate the channel responses for data subcarriers by using the channel responses for pilot subcarriers.
2. OFDM Wireless Communication with Dynamic Spectrum Access
This paper assumes that DSA wireless communication with subcarrier selection-type CSMA/CA  is employed. Table 1 summarizes the system parameters for the target DSA wireless communication system. This system is designed by taking into account its compatibility with OFDM in IEEE 802.11a  and IEEE 802.11g . In this condition, FFT size and the maximum bandwidth are twice as large as those of IEEE 802.11g. However the number of subcarriers used for data transmission is the same as that for IEEE 802.11g in order to avoid exclusive use of radio resources.
Figure 3 shows the OFDM frame structure. The OFDM frame consists of a physical layer convergence protocol (PLCP) preamble, which is used for synchronization detection, header symbols, that is, coded communication parameters, and data symbols including transmission data. The PLCP preamble is made up of a short preamble for timing detection and a long preamble for phase compensation. The short preamble is a ten times iteration of the reference pattern, and one reference pattern is 32 samples. In the receiver side, symbol timing detection is performed by using correlation between the reference pattern and the received short preamble signal. The long preamble signals are for phase compensation, whose amplitude and phase are known. The header symbol indicates the used modulation mode and the length of data symbols.
Figure 4 shows a block diagram of the target ODFM baseband transceiver with DSA . In the transmitter, the first process is forward error correction (FEC), which adds redundant data to input data so that the amount of data is set according to the coding rate. Interleaving is the second process, and it reorders data to avoid burst error. Modulated data are assigned to subcarriers in mapping process based on information on subcarrier assignment obtained from subcarrier level sensing. The mapping function is given by where and are subcarrier indices before and after mapping, respectively. While ranges from 0 to 127, ranges from 0 to 51. is a transform function based on subcarrier information obtained from subcarrier level carrier sensing. After mapping, IFFT transforms the frequency domain data to the time domain data. Here the number of data from mapping to IFFT is 52, and the size of IFFT is 128. Mapping should pass dummy data (i.e., 0’s) to IFFT for 76 () unused subcarriers. The increased number of input data to IFFT increases the computational cost to be more than that for conventional IEEE 802.11g. A cycle prefix (CP) whose length is greater than the channel delay spread is added prior to transmission by copying part of the IFFT output to mitigate the effects of intersymbol interference. Finally, through digital-analog converter (DAC), the samples are passed to a radio frequency (RF) unit that amplifies the signals and upconverts them to the required center frequency.
The receiver operates in reverse to the transmitter. In the receiver, the first process is timing synchronization. The timing synchronization process detects the beginning of a frame by calculating the correlation between the sequential data from the analog-digital converter (ADC) and the short preamble sequence, which is the known pattern signal. After symbol timing is synchronized, the added CP is removed, and FFT transforms the time domain data to the frequency domain data. Next, the demapping process, which is the reverse operation of mapping, selects 52 outputs of FFT based on subcarrier information from 128 subcarriers. In other words, the demapping process discards many data signals. The equalization process eliminates the effect of the transmission channel by using the channel transfer function estimated from long training sequences. Finally, Viterbi decoding process after demodulation and deinterleaving outputs the reconstructed version of the original data.
3. Fading Compensation
The received signals through the wireless channel are distorted by fading or noise as shown in Figure 5. Therefore fading compensation, which estimates and compensates received signal distortion, is necessary in order to accurately decode the received data.
This section describes the fading compensation for DSA we propose after explaining an example of preamble-based fading compensation  for OFDM transmission.
3.1. Preamble-Based Fading Compensation
Figure 6 shows an overview of preamble-based fading compensation. After FFT, received preamble signals are expressed as where is the index of used subcarriers, is the known preamble signal, and and represent ideal channel response and noise channel response, respectively . Received preamble signal is compared to known signal , and estimated channel response is calculated as The primary compensated signal is calculated by using : where is the received signal.
Next, secondary compensation with pilot subcarriers is carried out to cope with microvariations in channel responses in one OFDM symbol time. The estimated microvariation in channel response is expressed as where is the index of data subcarriers, is the index of pilot subcarriers and is that of the estimated microvariation for pilot signals, and is their interpolation function. The secondary compensated signals are given by where is the number of pilot subcarriers.
3.2. Fading Compensation for DSA
In the IEEE 802.11g, four of the subcarriers are dedicated to pilot signals in order to make coherent detection robust against frequency offsets and phase noise. These pilot signals are placed in ideal locations . Therefore, the arithmetic mean can be utilized as the function to estimate channel microvariations. However the arithmetic mean is not always efficient for OFDM with DSA since DSA utilizes different distributions of pilot subcarriers in different communications. This paper adopts piecewise linear interpolation as the interpolation function to estimate the channel responses for microvariations and evaluates the efficiency by comparing with the arithmetic mean. The details are described in the next subsection.
3.2.1. Microvariation Estimation with Piecewise Linear Interpolation
The estimated microvariation for the target subcarrier is calculated by linear interpolation between the estimated microvariation values for the left and right pilot subcarriers shown in Figure 7. The proposed interpolation function is given by where is the index of the target subcarrier, and correspond to the index of the left and right pilot subcarriers, and and are the estimated variation values for the left and right pilot subcarriers, respectively. and are expressed as
3.2.2. Preliminary Experiment
The preliminary experiment was carried out through software simulation to confirm that piecewise linear interpolation had an advantage over the arithmetic mean in respect to the Bit Error Rate (BER). Software with floating points emulates the behavior of the transceiver, but symbol timing error is not taken into consideration.
The Rayleigh fading model was used in the software simulation whose parameters are summarized in Table 2, and simulation conditions are listed in Table 3. Figure 8 plots the experiment results for BER, which is generally used as an indicator of the channel estimation accuracy. This indicates that piecewise linear interpolation is more efficient than the arithmetic mean, which is generally utilized in the 802.11a/g PHY. Therefore, we adopted piecewise linear interpolation to estimate microvariations.
4. Proposed Architecture of Fading Compensator for DSA
Figure 9 is a block diagram of the proposed fading compensator architecture. The proposed architecture consists of channel estimator, linear interpolator, coefficient calculator, linear projector, and five memories.
First, the coefficient calculator stores and obtained from mapping information in the memory and memory, respectively, while receiving PLCP preamble signals. Next, the primary compensated signals are input and stored in the data buffer. After all signals corresponding to one OFDM symbol have been stored, one data at a time is read from the data buffer. If the data is for the pilot, the channel estimator calculates the estimated microvariation value for the pilot, and the value is written to both left and right coefficient memories. After all estimated microvariation values for the pilots have been obtained, the Linear interpolator calculates each estimated microvariation value for data by piecewise linear interpolation with the distance between the target data subcarrier and two adjacent pilot subcarriers. Finally the secondary compensated signals for data are calculated from the primary compensated signals and estimated microvariation values for data in the Linear projector.
4.1. Channel Estimator
The block diagram of the channel estimator is shown in Figure 10.
This block treats as amplitude variation and phase shift in a polar coordinate system in order to enable microvariations to be easily calculated. Therefore, received signals in a rectangular coordinate system are transformed to in a polar coordinate system in this block. The transformation from a rectangular coordinate to a polar coordinate is given by
The input size of the function is restricted to 11-bit by comparing with so that the function can be constructed with a lookup table (LUT). All modules in this block adopt a pipelined architecture, and the square root and divider both take seven cycles each. Performing abs and square add take 1 cycle. As a result, the latency of this block is 15 cycles.
4.2. Coefficient Calculator
The two data and can be calculated with mapping information only. Therefore, the coefficient calculator obtains and and stores them in memories while receiving long preamble signals since the mapping information cannot be changed in a physical layer (PHY) frame.
The mapping information has two 128-bit data, where each bit corresponds to each subcarrier. The first data are called a utilization mask and indicate which subcarriers are used (1)/unused (0). The second are called a pilot mask and indicate which subcarriers are pilot subcarriers (1) or not (0). Figure 11 is the block diagram of the coefficient calculator. This block consists of subcarrier index generator, subcarrier type checking block, and coefficient generator. The subcarrier index generator and the coefficient generator are created by 7-bit counter, and the subcarrier type checking block is based on a barrel shifter. The two memories that have write access from this block are dual port RAMs since these memories also have read access from the linear interpolator. How and are determined by using these data is described hereinafter.
Figure 14 shows the contents of memories after all steps are executed.
This step includes forward and backward scanning of mapping information, and each scan takes 128 cycles since utilization of the subcarrier index, , as memory read address enables one cycle reading of pair coefficients from the Left and Right coefficient memories. The execution cycles of steps 2 and 4 are determined according to the pilot subcarrier arrangement. The maximum execution cycle is 129 cycles when only one of 128 subcarriers is dedicated to the pilot signal. The total execution cycles is at most 387 cycles since one cycle initialization and one cycle termination process are included.
4.3. Linear Interpolator
Figure 15 shows the block diagram of the linear interpolator. This block has four multipliers and three adders, and all of them have registered outputs. Therefore the linear interpolator has ten pipeline stages since this block has a dividor that has seven pipeline stages.
The linear interpolator performs two functions. One is preparing the left and right estimated microvariation values and . The other is calculation of the estimated microvariation value for data subcarriers .
First, the estimated microvariation values for pilot subcarriers are written in the left estimated microvariation memory, which is the output of the channel estimator. The entries corresponding to the subcarriers on the left of the first pilot subcarrier are written as zeroes. The entries for the other subcarriers are written as the estimated microvariation values for the nearest pilot subcarrier on the left. After all of the 128 entries have been written to, the right estimated microvariation values are obtained in the same way as the left estimated microvariation values by backward-scanning the left estimated microvariation memory and pilot mask. Each of the estimated microvariation values for the data subcarriers is calculated by linear interpolation (7) with the left and right coefficients and the left and right estimated microvariation values.
These operations are executed at 285 cycles including 128 cycles for writing, 128 cycles for scanning, 10 cycles for microvariation calculations, and 19 cycles for the initializing and terminating processes.
Figure 16 shows how to utilize the left and right estimated value.
4.4. Linear Projection Block
The secondary compensation is carried out by linear projection operation with the estimated microvariation value in the rectangular coordinate system. The linear projection operation is given by
The block diagram of linear projection block is shown in Figure 17. This block can input data every cycle and table access, and multiplication and addition take 1 cycle. As a result, the latency of this block is 4 cycles.
4.5. Execution Cycles and Operation Frequency
Table 4 summarizes the maximum execution cycles for each block in a fading compensation circuit.
When a block needs to terminate its process within OFDM symbol time (one ODFM symbol time is 4 s) during real-time operation, the minimum operation frequency, , for real-time operation is given by where is the number of execution cycles.
Since it is necessary for the coefficient calculator to terminate its process within two OFDM symbol times to receive all long preamble signals, the minimum operation frequency for real-time operation is 48.3 MHz . The execution time for the channel estimator, linear interpolator, and linear projector is 304 cycles for an OFDM symbol since they need to perform their operations for the same OFDM symbol. Therefore the minimum operation frequency is 76.0 MHz for these blocks.
As a result, the minimum operation frequency for the proposed fading compensator is 76.0 MHz since the minimum operation frequency of blocks excluding the coefficient calculator is 76.0 MHz and the minimum operation frequency of the coefficient calculator is 48.3 MHz.
5. FPGA Design of Fading Compensator
5.1. Implementation Result
The proposed architecture of the fading compensation circuit has been implemented in an FPGA (Xilinx Virtex-II xc2v3000), and Table 5 summarizes implementation results. This result surpasses the 76.0 MHz demanded for real-time operation.
5.2. Performance Evaluation
We simulated the performance of this fading compensator without Viterbi decoding under the conditions listed in Table 6 to confirm the behavior of the proposed architecture. Figure 18 shows the mapping condition in this simulation.
Figure 19 plots the simulation results for BER with hardware implementation. These results show that the hardware implementation achieves comparable performance to the 802.11a-based system without the diversity reported in  even though our architecture utilizes a discontinuous spectrum, and its performance is almost the same as the theoretical performance.
In this paper, a hardware architecture of fading compensation circuit for DSA was proposed. The proposed architecture adopted piecewise linear interpolation in order to accurately estimate channel responses for data subcarriers. Fading compensation for an OFDM symbol was executed in one OFDM symbol time in order to make increase of latency smaller. The results of FPGA implementation indicated that the proposed circuit occupied 1,577 slices and achieved 112 MHz operation frequency which overcame the 76.0 MHz demand for real-time operation on a single chip.
Future work is the performance evaluation of the OFDM transceiver with DSA combined with the proposed fading compensator.
This research has been supported by the Global COE program of the Ministry of Education, Culture, Sports, Science and Technology, Japan, under the title “Founding Ambient Information Society Infrastructure.”
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