Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

<table>Yield obtained from 3000 transistor-level simulations of SRAM<svg height="11.125" id="M241" style="vertical-align:-0.1638pt" version="1.1" viewbox="0 0 33.974998 11.125" width="33.974998" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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t98.5 -62.5q61 48 61 124q0 59 -29.5 90t-69.5 31zM248 20q46 0 76.5 33.5t30.5 89.5q0 50 -39 85.5t-110 71.5q-81 -54 -81 -137q0 -67 35.5 -105t87.5 -38z" id="x38"></path></g><g transform="matrix(.017,-0,0,-.017,11.996,10.862)"><path d="M528 54l-36 -38l-198 201l-198 -201l-36 38l197 200l-197 201l36 38l198 -202l198 202l36 -38l-197 -201z" id="xD7"></path></g><g transform="matrix(.017,-0,0,-.017,25.748,10.862)"><path d="M384 0h-275v27q67 5 81.5 18.5t14.5 68.5v385q0 38 -7.5 47.5t-40.5 10.5l-48 2v24q85 15 178 52v-521q0 -55 14.5 -68.5t82.5 -18.5v-27z" id="x31"></path></g>
</svg> for noncorrelated case.</table>

VLSI Design

fig20

Figure 20

Figure 20: Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits 