Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="984376.fig.0022a" src="https://static.hindawi.com/articles/vlsi/volume-2013/984376/figures/984376.fig.0022a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>MC without SB</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="984376.fig.0022b" src="https://static.hindawi.com/articles/vlsi/volume-2013/984376/figures/984376.fig.0022b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>QMC without SB</td></tr></table></td></tr><tr class="fig-image" id="c"><td><img alt="984376.fig.0022c" src="https://static.hindawi.com/articles/vlsi/volume-2013/984376/figures/984376.fig.0022c.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(c) </b>MC with SB</td></tr></table></td></tr><tr class="fig-image" id="d"><td><img alt="984376.fig.0022d" src="https://static.hindawi.com/articles/vlsi/volume-2013/984376/figures/984376.fig.0022d.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(d) </b>QMC with SB</td></tr></table></td></tr></table>

<table>Yield obtained from 3000 behavioural-level simulations of SRAM<svg height="11.125" id="M252" style="vertical-align:-0.1638pt" version="1.1" viewbox="0 0 42.137501 11.125" width="42.137501" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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</svg> for strongly correlated case, (a) MC without SB, (b) QMC without SB, (c) MC with SB, and (d) QMC with SB.</table>

VLSI Design

fig22

Figure 22

Figure 22: Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits 