Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

Table 1

Netlist for 2-input NAND gate using e-element.

e  𝑋 0 NAND(2) 𝐴 0 𝐵 0
+0.0	5.0 v
+0.5	4.8 v
+1.0	4.5 v
+4.0	0.5 v
+5.0	0.0 v