Improved Quantization Error Compensation Method for Fixed-Width Booth Multipliers

Table 7

Comparisons of performances with other methods.

Width (bits)	Multiplier	Area (μm^2)	Power (mW)	Delay (ns)	Power-delay product (mW·ns)
8	Ideal	3392	1.030	5.82	5.995
	[9]	2396	0.667	6.14	4.095
	[10]	2238	0.639	5.81	3.713
	[11]	2251	0.628	5.85	3.674
	[12]	2246	0.636	5.80	3.689
	[13]	2307	0.682	5.16	3.519
	SPPC	2242	0.633	5.22	3.304
10	Ideal	5154	1.293	6.60	8.534
	[9]	3758	0.833	6.97	5.806
	[10]	3479	0.789	6.26	4.940
	[11]	3395	0.777	6.62	5.144
	[12]	3252	0.715	6.13	4.383
	[13]	3351	0.842	5.91	4.982
	SPPC	3358	0.712	6.09	4.336
12	Ideal	7455	1.773	7.24	12.837
	[9]	5286	1.137	7.61	8.653
	[10]	5144	1.064	6.67	7.097
	[11]	5161	1.099	7.43	8.166
	[12]	4942	0.974	6.60	6.428
	[13]	4923	1.040	6.56	6.822
	SPPC	5056	1.012	6.63	6.710
16	Ideal	13554	2.562	8.06	20.650
	[9]	10058	1.563	8.41	12.145
	[10]	9692	1.486	7.84	11.650
	[11]	9508	1.476	8.08	11.926
	[12]	9390	1.310	7.81	10.230
	[13]	9297	1.403	7.58	10.635
	SPPC	9312	1.329	7.67	10.193