Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

Table 10

Cycle/access times versus issue width.

	IW 1	IW 2	IW 3	IW 4
Access	0 ps	195 ps	390 ps	585 ps
Time	(0)	(4.3)	(8.7)	(13.0)
Cycle	397 ps	592 ps	787 ps	982 ps
Time	(8.8)	(13.1)	(17.5)	(21.8)