Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

<div>(a) Input bit format of FPRM based Sum. (b) Input bit format of FPRM based Carry. (c)   .pla format of SRMDD based full-adder circuit.</div>

VLSI Design

Figure 9: Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits 