A Cache System Design for CMPs with Built-In Coherence Verification

<table class="table-group" id="tab4"><tr><td><table class="table"><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr class="thead"><td class="align_left">Group </td><td class="align_center">Rule for TACA</td></tr><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr><td class="align_left">3</td><td class="align_center">38, 52</td></tr><tr><td class="align_left">4</td><td class="align_center">46, 106, 116, 120, 166, 180, 235, 249</td></tr><tr><td class="align_left">5</td><td class="align_center">174, 239, 244, 253, 254</td></tr><tr class="table-tr"><td colspan="2"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

CA rules for single length 2-attractor CA (TACA).

VLSI Design

tab4

Table 4

Table 4: A Cache System Design for CMPs with Built-In Coherence Verification 