Research Article

A Cache System Design for CMPs with Built-In Coherence Verification

Table 8

Hardware requirements for .

ā€‰Scheme [2]
ā€‰MSIMESIMOESI
Number of coresNumber of FFsNumber of NANDsArea (units)Number of FFsNumber of NANDsNumber of XORsArea (units)Area (units)Area (units)
(1)(2)(3)(4)(5)(6)(7)(8)(9)(10)

1612824159478240161614416259840259840259840
3221152159787375523228832519680519680519680
644151215915431387264576641039360519680519680
1288043215929878491212811521282078720519680519680
25615928815959149838425623042564157440519680519680