Novel Verification Method for Timing Optimization Based on DPSO

<div>A typical path (red line) for the timing optimization process of a pipeline circuit in the Design Compiler (DC) tool beginning from the clock pin of flip-flop FF<sub>1</sub>, passing through logic circuits, and finally arriving at the D pin of flip-flop FF<sub>2</sub>.</div>

VLSI Design

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Figure 1

Figure 1: Novel Verification Method for Timing Optimization Based on DPSO 