Novel Verification Method for Timing Optimization Based on DPSO

Table 2

The average (Avg) timing delays obtained for MCNC benchmark circuits using three intelligent algorithms.

Circuits		TDPSO	SADPSO	WAGA	DPSO
		Avg/s	Avg/s	Avg/s	Avg/s
alu2	10/8	44	42	45	44
alu4	14/8	44	43	47	45
b9	41/21	9	9	9	9
cm85a	11/3	12	12	12	12
comp	32/3	23	22	23	23
count	36/16	22	21	22	22
dalu	75/16	25	25	26	26
k2	45/45	23	22	23	23
my_adder	33/17	51	49	53	51
pcler8	27/17	13	13	13	13
pcle	19/9	10	10	10	10
pm1	16/13	7	7	7	7
t481	16/1	20	20	20	20
terml	34/10	15	15	15	15
too_large	39/3	28	27	29	29
ttt2	25/21	12	12	12	12
vda	17/40	17	17	17	17

total number of inputs and outputs.