VLSI Design 
Volume 2008 (2008), Article ID 512946, 8 pages
doi:10.1155/2008/512946
Research Article

A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators

Tzung-Je Lee and Chua-Chin Wang

 Department of Electrical Engineering, National Sun Yat-Sen University, 70 Lian-Hai Road, Kaohsiung 80424, Taiwan
Received 28 January 2008; Revised 3 July 2008; Accepted 31 July 2008

Recommended by Wieslaw Kuzmicz

Abstract

A phase-locked loop (PLL) using separate regulators to reject the supply noise is proposed in this paper. Two regulators, REG1 and REG2, are used to prevent the supply noise from the charge pump (CP) and the voltage-controlled oscillator (VCO), respectively. By using separate regulators, the area and the power consumption of the regulator can be reduced. Moreover, the jitter of the proposed PLL is proven on silicon to be less sensitive to the supply noise. The proposed PLL is fabricated using a typical 0.35 μm 2P4M CMOS process. The peak-to-peak jitter (P2P jitter) of the proposed PLL is measured to be 81.8 ps at 80 MHz when a 250 mVrms supply noise is added. By contrast, the P2P jitter is measured to be 118.2 ps without the two regulators when the same supply noise is coupled.