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Citations to this Journal [1,501 citations: 1–100 of 1,374 articles]

Articles published in VLSI Design have been cited 1,501 times. The following is a list of the 1,374 articles that have cited the articles published in VLSI Design.

  • Adel Soudani, and Gilles Sicard, “Hardware compression scheme based on low complexity arithmetic encoding for low power image transmission over WSNs,” Aeu-International Journal of Electronics and Communications, vol. 68, no. 3, pp. 193–200, 2014. View at Publisher · View at Google Scholar
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  • Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, and Maurizio Zamboni, “Simulation and design of an UWB imaging system for breast cancer detection,” Integration, the VLSI Journal, 2014. View at Publisher · View at Google Scholar
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  • Xiangyu Zhou, Francesco Bertazzi, Michele Goano, Giovanni Ghione, and Enrico Bellotti, “Deriving k·p parameters from full-Brillouin-zone descriptions: A finite-element envelope function model for quantum-confined wurtzite nanostructures,” Journal of Applied Physics, vol. 116, no. 3, pp. 033709, 2014. View at Publisher · View at Google Scholar
  • Vijay Kumar Sharma, and Manisha Pattanaik, “Techniques For Low Leakage Nanoscale Vlsi Circuits: A Comparative Study,” Journal of Circuits, Systems and Computers, pp. 1450061, 2014. View at Publisher · View at Google Scholar
  • Jan-Frederik Mennemann, and Ansgar Jüngel, “Perfectly Matched Layers versus discrete transparent boundary conditions in quantum device simulations,” Journal of Computational Physics, 2014. View at Publisher · View at Google Scholar
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  • Bichlien H. Nguyen, David Kesselring, Eden Tesfu, and Kevin D. Moeller, “Microelectrode Arrays: A General Strategy for Using Oxidation Reactions To Site Selectively Modify Electrode Surfaces,” Langmuir, pp. 140218080037000, 2014. View at Publisher · View at Google Scholar
  • Farhad Fakhar-Izadi, and Mehdi Dehghan, “A spectral element method using the modal basis and its application in solving second-order nonlinear partial differential equations,” Mathematical Methods in the Applied Sciences, 2014. View at Publisher · View at Google Scholar
  • I. Hameem Shanavas, and R. K. Gnanamurthy, “Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm,” Mathematical Problems in Engineering, vol. 2014, pp. 1–15, 2014. View at Publisher · View at Google Scholar
  • Yabin Zhang, and Paolo Emilio Bagnoli, “A modeling methodology for thermal analysis of the PCB structure,” Microelectronics Journal, vol. 45, no. 8, pp. 1033–1052, 2014. View at Publisher · View at Google Scholar
  • K. Somasundaram, Juha Plosila, and N. Viswanathan, “Deadlock free routing algorithm for minimizing congestion in a Hamiltonian connected recursive 3D-NoCs,” Microelectronics Journal, vol. 45, no. 8, pp. 989–1000, 2014. View at Publisher · View at Google Scholar
  • Hao Shu, Pei-jun Ma, Jiang-yi Shi, Zhao Xu, and Lin-an Yang, “SRNoC: A novel high performance Shared-Resource routing scheme for Network-on-Chip,” Microelectronics Journal, vol. 45, no. 8, pp. 1103–1117, 2014. View at Publisher · View at Google Scholar
  • Roberto Giorgi, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Rahul Gayatri, Sylvain Girbal, Daniel Goodman, Behran Khan, Souad Koliaï, Joshua Landwehr, Nhat Minh Lê, Feng Li, Mikel Lujàn, Avi Mendelson, Laurent Morin, Nacho Navarro, Tomasz Patejko, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Ian Watson, Sebastian Weis, Stéphane Zuckerman, and Mateo Valero, “TERAFLUX: Harnessing Dataflow in Next Generation Teradevices,” Microprocessors and Microsystems, 2014. View at Publisher · View at Google Scholar
  • Guangda Zhang, Wei Song, Jim Garside, Javier Navaridas, and Zhiying Wang, “Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes,” Microprocessors and Microsystems, 2014. View at Publisher · View at Google Scholar
  • Vishnu P. Nambiar, Mohamed Khalil-Hani, Riadh Sahnoun, and M.N. Marsono, “Hardware Implementation of Evolvable Block-Based Neural Networks Utilizing a Cost Efficient Sigmoid-Like Activation Function,” Neurocomputing, 2014. View at Publisher · View at Google Scholar
  • Vishnu P. Nambiar, Mohamed Khalil-Hani, M.N. Marsono, and C.W. Sia, “Optimization of Structure and System Latency in Evolvable Block-Based Neural Networks using Genetic Algorithm,” Neurocomputing, 2014. View at Publisher · View at Google Scholar
  • Kevin D. Moeller, “Electrochemically Generated Organometallic Reagents and Site-Selective Synthesis on a Microelectrode Array,” Organometallics, pp. 140624160930009, 2014. View at Publisher · View at Google Scholar
  • A. R. Seadawy, “Stability analysis for two-dimensional ion-acoustic waves in quantum plasmas,” Physics of Plasmas, vol. 21, no. 5, pp. 052107, 2014. View at Publisher · View at Google Scholar
  • D. Chitra, and T. Manigandan, “Low Power Adder Based Digital Filter for QRS Detector,” Scientific World Journal, 2014. View at Publisher · View at Google Scholar
  • Tareq Hasan Khan, “White and narrow band image compressor based on a new color space for capsu le endoscopy,” Signal Processing-Image Communication, vol. 29, no. 3, pp. 345–360, 2014. View at Publisher · View at Google Scholar
  • Jeffrey Chan, Samantha Lam, and Conor Hayes, “Generalised blockmodelling of social and relational networks using evolutionary computing,” Social Network Analysis and Mining, vol. 4, no. 1, 2014. View at Publisher · View at Google Scholar
  • Johannes Wendeberg, and Christian Schindelhauer, “Polynomial-time approximation algorithms for anchor-free TDoA localization,” Theoretical Computer Science, 2014. View at Publisher · View at Google Scholar
  • Khader Mohammad, Ahsan Kabeer, and Tarek Taha, “On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding,” VLSI Design, vol. 2014, pp. 1–14, 2014. View at Publisher · View at Google Scholar
  • Chaochao Feng, Xueqian Zhao, and Axel Jantsch, “Methods for Fault Tolerance in Networks-on-Chip,” Acm Computing Surveys, vol. 46, no. 1, 2013. View at Publisher · View at Google Scholar
  • Yosi Ben Asher, “Hybrid Type Legalization for a Sparse SIMD Instruction Set,” Acm Transactions on Architecture and Code Optimization, vol. 10, no. 3, 2013. View at Publisher · View at Google Scholar
  • Amit Agarwal, Jason Cong, and Brian Tagiku, “The Survivability of Design-Specific Spare Placement in FPGA Architectures with High Defect Rates,” Acm Transactions on Design Automation of Electronic Systems, vol. 18, no. 2, 2013. View at Publisher · View at Google Scholar
  • Samuel Rodrigo, Davide Bertozzi, Tor Skeie, Francisco Gilabert, Alessandro Strano, and Frank Olaf Sem-Jacobsen, “Enabling Power Efficiency through Dynamic Rerouting On-Chip,” Acm Transactions On Embedded Computing Systems, vol. 12, no. 4, 2013. View at Publisher · View at Google Scholar
  • Matthew A. Smith, Claire N. Bedbrook, Timothy Wu, and Frances H. Arnold, “H. jecorina cellobiohydrolase I stabilizing mutations identified using non-contiguous recombination,” ACS Synthetic Biology, pp. 130520144749009, 2013. View at Publisher · View at Google Scholar
  • D. S. H. Ram, M. C. Bhuvaneswari, and S. Umadevi, “Improved Low Power FPGA Binding of Datapaths from Data Flow Graphs with NSGA II -based Schedule Selection,” Advances in Electrical and Computer Engineering, vol. 13, no. 4, pp. 85–92, 2013. View at Publisher · View at Google Scholar
  • Alessandro Lo Schiavo, “Predicting nonlinear distortion in multistage amplifiers and g(m)-C filters,” Analog Integrated Circuits and Signal Processing, vol. 77, no. 3, pp. 483–493, 2013. View at Publisher · View at Google Scholar
  • Mehdi Dehghan, and Faezeh Emami-Naeini, “The Sinc-collocation and Sinc-Galerkin methods for solving the two-dimensional Schrödinger equation with nonhomogeneous boundary conditions,” Applied Mathematical Modelling, 2013. View at Publisher · View at Google Scholar
  • M. Madheswaran, and T. Menakadevi, “An Improved Direct Digital Synthesizer Using Hybrid Wave Pipelining and COR DIC algorithm for Software Defined Radio,” Circuits Systems and Signal Processing, vol. 32, no. 3, pp. 1219–1238, 2013. View at Publisher · View at Google Scholar
  • Peiman Keshavarzian, and Rahil Sarikhani, “A Novel CNTFET-based Ternary Full Adder,” Circuits, Systems, and Signal Processing, vol. 33, no. 3, pp. 665–679, 2013. View at Publisher · View at Google Scholar
  • S. Sabarathinam, K. Thamilmaran, L. Borkowski, P. Perlikowski, P. Brzeski, A. Stefanski, and T. Kapitaniak, “Transient chaos in two coupled, dissipatively perturbed Hamiltonian Duffing oscillators,” Communications in Nonlinear Science and Numerical Simulation, 2013. View at Publisher · View at Google Scholar
  • Ke Qiu, and Zhizhang Shen, “A Generating Function Approach to the Edge Surface Area of the Arrangement Graphs,” Computer Journal, vol. 56, no. 7, pp. 871–881, 2013. View at Publisher · View at Google Scholar
  • Xavier Antoine, Weizhu Bao, and Christophe Besse, “Computational methods for the dynamics of the nonlinear Schrödinger/Gross–Pitaevskii equations,” Computer Physics Communications, 2013. View at Publisher · View at Google Scholar
  • O. Muscato, and V. Di Stefano, “Hydrodynamic simulation of a n + − n − n + silicon nanowire,” Continuum Mechanics and Thermodynamics, 2013. View at Publisher · View at Google Scholar
  • Mibaile Justin, Gambo Betchewe, Serge Y. Doka, J. Yves Effa, and Timoleon Crepin Kofane, “Chaos in semiconductor band-trap impact ionization,” Current Applied Physics, 2013. View at Publisher · View at Google Scholar
  • Mirgender Kumar, Sarvesh Dubey, Pramod Kumar Tiwari, and S. Jit, “Analytical Modeling and Simulation of Subthreshold Characteristics of Back-Gated SSGOI and SSOI MOSFETs: A Comparative Study,” Current Applied Physics, 2013. View at Publisher · View at Google Scholar
  • Gayatri Mehta, and Alex K. Jones, “Implementation and validation of architectural space exploration techniques for domain-specific reconfigurable computing,” Design Automation for Embedded Systems, 2013. View at Publisher · View at Google Scholar
  • A. A. Zlotnik, and I. A. Zlotnik, “Finite element method with discrete transparent boundary conditions for the one-dimensional nonstationary Schrödinger equation,” Doklady Mathematics, vol. 86, no. 3, pp. 750–755, 2013. View at Publisher · View at Google Scholar
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  • Ted H. Szymanski, “Max-Flow Min-Cost Routing in a Future-Internet with Improved QoS Guarantees,” Ieee Transactions on Communications, vol. 61, no. 4, pp. 1485–1497, 2013. View at Publisher · View at Google Scholar
  • Joao Marques-Silva, “A Two-Variable Model for SAT-Based ATPG,” Ieee Transactions on Computer-Aided Design of Integrated Circuits and Syste, vol. 32, no. 12, pp. 1943–1956, 2013. View at Publisher · View at Google Scholar
  • Michel A. Kinsy, Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, G. Edward Suh, and Srinivas Devadas, “Optimal and Heuristic Application-Aware Oblivious Routing,” Ieee Transactions On Computers, vol. 62, no. 1, pp. 59–73, 2013. View at Publisher · View at Google Scholar
  • Henry J. Duwe, Michael J. Schulte, and Katherine Compton, “Modular Design of High-Throughput, Low-Latency Sorting Units,” Ieee Transactions on Computers, vol. 62, no. 7, pp. 1389–1402, 2013. View at Publisher · View at Google Scholar
  • Zhiyang Guo, and Yuanyuan Yang, “Efficient All-to-All Broadcast in Gaussian On-Chip Networks,” Ieee Transactions On Computers, vol. 62, no. 10, pp. 1959–1971, 2013. View at Publisher · View at Google Scholar
  • Santiago Mazuelas, Giorgio M. Vitetta, and Moe Z. Win, “On the Performance Limits of Map-Aware Localization,” Ieee Transactions on Information Theory, vol. 59, no. 8, pp. 5023–5038, 2013. View at Publisher · View at Google Scholar
  • Faizal Arya Samman, Thomas Hollstein, and Manfred Glesner, “Runtime contention and bandwidth-aware adaptive routing selection strategies for networks-on-chip,” IEEE Transactions on Parallel and Distributed Systems, vol. 24, no. 7, pp. 1411–1421, 2013. View at Publisher · View at Google Scholar
  • Marcello Pelillo, “A Game-Theoretic Approach to Hypergraph Clustering,” Ieee Transactions on Pattern Analysis and Machine Intelligence, vol. 35, no. 6, pp. 1312–1327, 2013. View at Publisher · View at Google Scholar
  • Abbas Eslami Kiasari, Zhonghai Lu, and Axel Jantsch, “An analytical latency model for networks-on-chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 1, pp. 113–123, 2013. View at Publisher · View at Google Scholar
  • Sehun Kook, Hyun Woo Choi, and Abhijit Chatterjee, “Low-resolution DAC-driven linearity testing of higher resolution ADCs using polynomial fitting measurements,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 3, pp. 454–464, 2013. View at Publisher · View at Google Scholar
  • Shingo Yoshizawa, Yasuyuki Hatakawa, Tomoko Matsumoto, Satoshi Konishi, and Yoshikazu Miyanaga, “A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using A rrayed Pipelined Processing,” Ieice Transactions on Fundamentals of Electronics Communications and Comput, vol. E96A, no. 11, pp. 2114–2119, 2013. View at Publisher · View at Google Scholar
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  • Joyashree Bag, and Subir Kumar Sarkar, “Development and VLSI implementation of a data security scheme for RFID system using programmable cellular automata,” International Journal of Radio Frequency Identification Technology and Applications, vol. 4, no. 2, pp. 197–211, 2013. View at Publisher · View at Google Scholar
  • Subhra Dhar, Manisha Pattanaik, and P. Rajaram, “Analysing ION/IOFF in ultradeep-submicron CMOS devices using grooved nMOSFETs for low-power applications,” International Journal of Signal and Imaging Systems Engineering, vol. 6, no. 1, pp. 24–30, 2013. View at Publisher · View at Google Scholar
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  • Maurizio Martina, and Guido Masera, “Improving Network-on-Chip-based Turbo Decoder Architectures,” Journal of Signal Processing Systems, 2013. View at Publisher · View at Google Scholar
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