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Citations to this Journal [1,558 citations: 101–200 of 1,427 articles]

Articles published in VLSI Design have been cited 1,558 times. The following is a list of the 1,427 articles that have cited the articles published in VLSI Design.

  • Zhiyang Guo, Yuanyuan Yang, and Zhemin Zhang, “Efficient All-to-All Broadcast in Gaussian On-Chip Networks,” Ieee Transactions On Computers, vol. 62, no. 10, pp. 1959–1971, 2013. View at Publisher · View at Google Scholar
  • Santiago Mazuelas, Giorgio M. Vitetta, and Moe Z. Win, “On the Performance Limits of Map-Aware Localization,” Ieee Transactions on Information Theory, vol. 59, no. 8, pp. 5023–5038, 2013. View at Publisher · View at Google Scholar
  • John D. Cressler, “Radiation Effects in SiGe Technology,” Ieee Transactions On Nuclear Science, vol. 60, no. 3, pp. 1992–2014, 2013. View at Publisher · View at Google Scholar
  • Faizal Arya Samman, Thomas Hollstein, and Manfred Glesner, “Runtime contention and bandwidth-aware adaptive routing selection strategies for networks-on-chip,” IEEE Transactions on Parallel and Distributed Systems, vol. 24, no. 7, pp. 1411–1421, 2013. View at Publisher · View at Google Scholar
  • Marcello Pelillo, “A Game-Theoretic Approach to Hypergraph Clustering,” Ieee Transactions on Pattern Analysis and Machine Intelligence, vol. 35, no. 6, pp. 1312–1327, 2013. View at Publisher · View at Google Scholar
  • Abbas Eslami Kiasari, Zhonghai Lu, and Axel Jantsch, “An analytical latency model for networks-on-chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 1, pp. 113–123, 2013. View at Publisher · View at Google Scholar
  • Sehun Kook, Hyun Woo Choi, and Abhijit Chatterjee, “Low-resolution DAC-driven linearity testing of higher resolution ADCs using polynomial fitting measurements,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 3, pp. 454–464, 2013. View at Publisher · View at Google Scholar
  • Kosuke Shimazaki, Shingo Yoshizawa, Yasuyuki Hatakawa, Tomoko Matsumoto, Satoshi Konishi, and Yoshikazu Miyanaga, “A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing,” Ieice Transactions on Fundamentals of Electronics Communications and Comput, vol. E96A, no. 11, pp. 2114–2119, 2013. View at Publisher · View at Google Scholar
  • Kyungsoo Lee, and Tohru Ishihara, “DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96.A, no. 12, pp. 2660–2667, 2013. View at Publisher · View at Google Scholar
  • Mohammad Hossein Moaiyeri, Reza Faghih Mirzaee, Akbar Doostaregan, Keivan Navi, and Omid Hashemipour, “A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits,” Iet Computers and Digital Techniques, vol. 7, no. 4, pp. 167–181, 2013. View at Publisher · View at Google Scholar
  • Ming-Chien Yang, “Conditional diagnosability of matching composition networks under the MM∗ model,” Information Sciences, vol. 233, pp. 230–243, 2013. View at Publisher · View at Google Scholar
  • Wei Wang, Sujian Li, Jiwei Li, Wenjie Li, and Furu Wei, “Exploring hypergraph-based semi-supervised ranking for query-oriented summarization,” Information Sciences, vol. 237, pp. 271–286, 2013. View at Publisher · View at Google Scholar
  • Mohammed H. Alser, Maher M. Assaad, and Fawnizu A. Hussin, “A wide-range programmable frequency synthesizer based on a finite state machine filter,” International Journal of Electronics, vol. 100, no. 11, pp. 1546–1556, 2013. View at Publisher · View at Google Scholar
  • Sneh Lata Murotiya, and Anu Gupta, “Design of CNTFET-based 2-bit ternary ALU for nanoelectronics,” International Journal of Electronics, pp. 1–14, 2013. View at Publisher · View at Google Scholar
  • Joyashree Bag, and Subir Kumar Sarkar, “Development and VLSI implementation of a data security scheme for RFID system using programmable cellular automata,” International Journal of Radio Frequency Identification Technology and Applications, vol. 4, no. 2, pp. 197–211, 2013. View at Publisher · View at Google Scholar
  • Subhra Dhar, Manisha Pattanaik, and P. Rajaram, “Analysing ION/IOFF in ultradeep-submicron CMOS devices using grooved nMOSFETs for low-power applications,” International Journal of Signal and Imaging Systems Engineering, vol. 6, no. 1, pp. 24–30, 2013. View at Publisher · View at Google Scholar
  • A. K. Pandey, R. A. Mishra, and R. K. Nagaria, “Leakage Power Analysis of Domino XOR Gate,” ISRN Electronics, vol. 2013, pp. 1–7, 2013. View at Publisher · View at Google Scholar
  • Shima Mehrabi, Reza Faghih Mirzaee, Keivan Navi, and Omid Hashemipour, “A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell,” ISRN Electronics, vol. 2013, pp. 1–8, 2013. View at Publisher · View at Google Scholar
  • Shipra Upadhyay, R. A. Mishra, R. K. Nagaria, and S. P. Singh, “DFAL: Diode-Free Adiabatic Logic Circuits,” ISRN Electronics, vol. 2013, pp. 1–12, 2013. View at Publisher · View at Google Scholar
  • Ralf Granzner, Frank Schwierz, Sonja Engert, and Hannes Töpfer, “Performance Fluctuations in 10-nm Trigate Metal–Oxide–Semiconductor Field-Effect Transistors: Impact of the Channel Geometry,” Japanese Journal of Applied Physics, vol. 52, no. 4S, pp. 04CC19, 2013. View at Publisher · View at Google Scholar
  • Takamitsu Ishihara, and Koichi Kato, “Theoretical prediction of universal curves for carrier transport in Si/SiO[sub 2](100) interfaces,” Journal of Applied Physics, vol. 114, no. 5, pp. 053713, 2013. View at Publisher · View at Google Scholar
  • Larysa Titarenko, Raisa Malcheva, and Kyryll Soldatov, “Hardware Reduction In Fpga-Based Moore Fsm,” Journal of Circuits Systems and Computers, vol. 22, no. 3, 2013. View at Publisher · View at Google Scholar
  • Ai-Qin Zeng, Qin-Qin Li, Li-Ye Cheng, and Xin-Quan Lai, “Dynamic Pulse Integrating Circuit For Infrared Receivers,” Journal of Circuits Systems and Computers, vol. 22, no. 7, 2013. View at Publisher · View at Google Scholar
  • Samira Sayedsalehi, Mohammad Hossein Moaiyeri, and Keivan Navi, “Design of Efficient and Testable n-Input Logic Gates in Quantum-Dot Cellular Automata,” Journal of Computational and Theoretical Nanoscience, vol. 10, no. 10, pp. 2347–2353, 2013. View at Publisher · View at Google Scholar
  • Jan-Frederik Mennemann, Ansgar Jüngel, and Hans Kosina, “Transient Schrödinger–Poisson simulations of a high-frequency resonant tunneling diode oscillator,” Journal of Computational Physics, vol. 239, pp. 187–205, 2013. View at Publisher · View at Google Scholar
  • Giovanni Stracquadanio, Vittorio Romano, and Giuseppe Nicosia, “Semiconductor device design using the BiMADS algorithm,” Journal of Computational Physics, vol. 242, pp. 304–320, 2013. View at Publisher · View at Google Scholar
  • A. Mahabadi, S.M. Zahedi, and A. Khonsari, “Reliable energy-aware application mapping and voltage–frequency island partitioning for GALS-based NoC,” Journal of Computer and System Sciences, vol. 79, no. 4, pp. 457–474, 2013. View at Publisher · View at Google Scholar
  • Mohammad Arjomand, S. Hamid Amiri, and Hamid Sarbazi-Azad, “Efficient genetic based topological mapping using analytical models for on-chip networks,” Journal of Computer and System Sciences, vol. 79, no. 4, pp. 492–513, 2013. View at Publisher · View at Google Scholar
  • Ved Prakash Bhardwaj, and Nitin, “Message Broadcasting via a New Fault Tolerant Irregular Advance Omega Network in Faulty and Nonfaulty Network Environments,” Journal of Electrical and Computer Engineering, vol. 2013, pp. 1–16, 2013. View at Publisher · View at Google Scholar
  • Tie-Bin Wu, Heng-Zhu Liu, Peng-Xia Liu, Dong-Sheng Guo, and Hai-Ming Sun, “A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic,” Journal of Electronic Testing, 2013. View at Publisher · View at Google Scholar
  • A. K. Pandey, R. A. Mishra, and R. K. Nagaria, “Static Switching Dynamic Buffer Circuit,” Journal of Engineering, vol. 2013, pp. 1–11, 2013. View at Publisher · View at Google Scholar
  • Maher Assaad, Mohammed H. Alser, and Amine Bermak, “Design and characterization of low power and low noise truly all-digital clock and data recovery circuit for SERDES devices,” Journal of Low Power Electronics, vol. 9, no. 1, pp. 63–72, 2013. View at Publisher · View at Google Scholar
  • Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, “Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor,” Journal of Semiconductor Technology and Science, vol. 13, no. 5, pp. 500–510, 2013. View at Publisher · View at Google Scholar
  • Maurizio Martina, and Guido Masera, “Improving Network-on-Chip-based Turbo Decoder Architectures,” Journal of Signal Processing Systems, 2013. View at Publisher · View at Google Scholar
  • Akram Ben Ahmed, and Abderazek Ben Abdallah, “Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC),” Journal of Supercomputing, vol. 66, no. 3, pp. 1507–1532, 2013. View at Publisher · View at Google Scholar
  • M.H. Neishaburi, and Zeljko Zilic, “NISHA: A fault-tolerant NoC router enabling deadlock-free Interconnection of Subnets in Hierarchical Architectures,” Journal of Systems Architecture, 2013. View at Publisher · View at Google Scholar
  • Wei Jiang, Zhenlin Guo, Yue Ma, and Nan Sang, “Measurement-Based Research on Cryptographic Algorithms for Embedded Real-time Systems,” Journal of Systems Architecture, 2013. View at Publisher · View at Google Scholar
  • N. Janakiraman, and P. Nirmal Kumar, “Multi-Objective Module Partitioning design for Dynamic and Partial Reconfigurable System-on-Chip Using Genetic Algorithm,” Journal of Systems Architecture, 2013. View at Publisher · View at Google Scholar
  • Alexandra Aguiar, Sergio Johann Filho, Felipe Magalhaes, and Fabiano Hessel, “On the design space exploration through the Hellfire Framework,” Journal of Systems Architecture, 2013. View at Publisher · View at Google Scholar
  • Matthew D. Graaf, Libo Hu, and Kevin D. Moeller, “The Use of UV-Cross-Linkable Di-Block Copolymers as Functional Reaction Surfaces for Microelectrode Arrays,” Journal Of The Electrochemical Society, vol. 160, no. 7, pp. G3020–G3029, 2013. View at Publisher · View at Google Scholar
  • A. Bhattacharjee, and A. Sutradhar, “Nonparametric Identification of Glucose-Insulin Process in IDDM Patient with Multi-meal Disturbance,” Journal of The Institution of Engineers (India): Series B, 2013. View at Publisher · View at Google Scholar
  • Sanghoon Jo, and Ja-Young Kang, “Hyperbolic Location Estimation of Aircraft with Motion in a Plane,” Journal of the Korean Society for Aviation and Aeronautics, vol. 21, no. 2, pp. 33–39, 2013. View at Publisher · View at Google Scholar
  • David K. Ferry, “Evolution of Physics and Chemistry of Surfaces and Interfaces: A Perspective of the Last 40 Years,” Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, vol. 31, no. 4, pp. 048501, 2013. View at Publisher · View at Google Scholar
  • Neha Verma, Mridula Gupta, R.S. Gupta, and Jyotika Jogi, “Quantum Modeling of Nanoscale Symmetric Double-Gate InAlAs/InGaAs/InP HEMT,” JSTS:Journal of Semiconductor Technology and Science, vol. 13, no. 4, pp. 342–354, 2013. View at Publisher · View at Google Scholar
  • Martin Frank, Cory D. Hauck, and Edgar Olbrant, “Perturbed, entropy-based closure for radiative transfer,” Kinetic and Related Models, vol. 6, no. 3, pp. 557–587, 2013. View at Publisher · View at Google Scholar
  • Kishore Kumar Muchherla, Jai Ganesh Kumar, and Janet M. Wang Roveda, “Cluster based dynamic area-array I/O planning for flip chip technology,” Microelectronic Engineering, 2013. View at Publisher · View at Google Scholar
  • Habib Rastegar, Saeed Saryazdi, and Ahmad Hakimi, “A low power and high linearity UWB low noise amplifier (LNA) for 3.1–10.6GHz wireless applications in 0.13μm CMOS process,” Microelectronics Journal, vol. 44, no. 3, pp. 201–209, 2013. View at Publisher · View at Google Scholar
  • Xicai Yue, “Determining the reliable minimum unit capacitance for the DAC capacitor array of SAR ADCs,” Microelectronics Journal, vol. 44, no. 6, pp. 473–478, 2013. View at Publisher · View at Google Scholar
  • K. Jabeur, I. O’Connor, and N. Yakymets, “Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET),” Microelectronics Journal, 2013. View at Publisher · View at Google Scholar
  • M. Turrillas, A. Cortés, I. Vélez, J.F. Sevillano, and A. Irizar, “An area-efficient Radix 28 FFT algorithm for DVB-T2 receivers,” Microelectronics Journal, 2013. View at Publisher · View at Google Scholar
  • Muhammad Aqeel Wahlah, and Kees Goossens, “TeMNOT: A test methodology for the non-intrusive online testing of FPGA with hardwired network on chip,” Microprocessors and Microsystems, vol. 37, no. 2, pp. 129–146, 2013. View at Publisher · View at Google Scholar
  • Ciprian Radu, Md. Shahriar Mahbub, and Lucian Vintan, “Developing Domain-Knowledge Evolutionary Algorithms for Network-on-Chip Application Mapping,” Microprocessors and Microsystems, vol. 37, no. 1, pp. 65–78, 2013. View at Publisher · View at Google Scholar
  • B. Lakshmi, and A.S. Dhar, “VLSI architecture for parallel radix-4 CORDIC,” Microprocessors and Microsystems, vol. 37, no. 1, pp. 79–86, 2013. View at Publisher · View at Google Scholar
  • M. Maheswari, and G. Seetharaman, “Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links,” Microprocessors and Microsystems, 2013. View at Publisher · View at Google Scholar
  • Syed. M.A.H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, and Hannu Tenhunen, “Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes,” Microprocessors and Microsystems, 2013. View at Publisher · View at Google Scholar
  • Faizal Arya Samman, “Runtime Connection-Oriented Guaranteed-Bandwidth Network-on-Chip with Extra Multicast Communication Service,” Microprocessors and Microsystems, 2013. View at Publisher · View at Google Scholar
  • Onur Derin, Emanuele Cannella, Giuseppe Tuveri, Paolo Meloni, Todor Stefanov, Leandro Fiorin, Luigi Raffo, and Mariagiovanna Sami, “A System-level Approach to Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project,” Microprocessors and Microsystems, 2013. View at Publisher · View at Google Scholar
  • Lech Jozwiak, Menno Lindwer, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastian Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo, and Giuseppe Notarangelo, “ASAM: Automatic architecture synthesis and application mapping,” Microprocessors and Microsystems, vol. 37, no. 8, pp. 1002–1019, 2013. View at Publisher · View at Google Scholar
  • Lech Jóźwiak, and Yahya Jan, “Design of Massively Parallel Hardware Multi-Processors for Highly-demanding Embedded Applications,” Microprocessors and Microsystems, 2013. View at Publisher · View at Google Scholar
  • Yahya Jan, and Lech Jóźwiak, “Processor Architecture Exploration and Synthesis of Massively Parallel Multi-processor Accelerators in Application to LDPC Decoding,” Microprocessors and Microsystems, 2013. View at Publisher · View at Google Scholar
  • A.H. Bhrawy, M.A. Abdelkawy, and Anjan Biswas, “Optical solitons in (1+1) and (2+1) dimensions,” Optik - International Journal for Light and Electron Optics, 2013. View at Publisher · View at Google Scholar
  • Jake A. Smith, and Kevin D. Moeller, “Oxidative Cyclizations, the Synthesis of Aryl-Substituted C-Glycosides, and the Role of the Second Electron Transfer Step,” Organic Letters, pp. 131107103505000, 2013. View at Publisher · View at Google Scholar
  • Xiaohang Wang, Peng Liu, Mei Yang, and Yingtao Jiang, “Avoiding request–request type message-dependent deadlocks in networks-on-chips,” Parallel Computing, 2013. View at Publisher · View at Google Scholar
  • Frank Grossmann, “Discrete transparent boundary conditions for the time-dependent Schrödinger equation: an explicit formulation,” Physica Scripta, vol. 88, no. 6, pp. 065014, 2013. View at Publisher · View at Google Scholar
  • YunPeng Liu, XiaoBin Tang, ZhiHeng Xu, Liang Hong, Peng Wang, and Da Chen, “Optimization and temperature effects on sandwich betavoltaic microbattery,” Science China Technological Sciences, 2013. View at Publisher · View at Google Scholar
  • O Muscato, and V Di Stefano, “Electro-thermal behaviour of a sub-micron silicon diode,” Semiconductor Science and Technology, vol. 28, no. 2, pp. 025021, 2013. View at Publisher · View at Google Scholar
  • V. D. Camiola, and V. Romano, “2DEG-3DEG Charge Transport Model for MOSFET Based on the Maximum Entropy Principle,” SIAM Journal on Applied Mathematics, vol. 73, no. 4, pp. 1439–1459, 2013. View at Publisher · View at Google Scholar
  • H. Yviquel, J. Boutellier, M. Raulet, and E. Casseau, “Automated design of networks of Transport-Triggered Architecture processors using Dynamic Dataflow Programs,” Signal Processing: Image Communication, 2013. View at Publisher · View at Google Scholar
  • Hamideh Etemadnia, Khaled Abdelghany, and Ahmed Hassan, “A network partitioning methodology for distributed traffic management applications,” Transportmetrica A: Transport Science, pp. 1–15, 2013. View at Publisher · View at Google Scholar
  • Shipra Upadhyay, R. K. Nagaria, and R. A. Mishra, “Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic,” VLSI Design, vol. 2013, pp. 1–9, 2013. View at Publisher · View at Google Scholar
  • Bisrat Tafesse, and Venkatesan Muthukumar, “Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration,” VLSI Design, vol. 2013, pp. 1–16, 2013. View at Publisher · View at Google Scholar
  • Gracieli Posser, Guilherme Flach, Gustavo Wilke, and Ricardo Reis, “Tradeoff between delay and area in gate sizing using Geometric Programming,” 2012 IEEE 3rd Latin American Symposium on Circuits and Systems, LASCAS 2012 - Conference Proceedings, 2012. View at Publisher · View at Google Scholar
  • Radu Stefan, Ashkan Beyranvand Nejad, and Kees Goossens, “Online allocation for contention-free-routing NoCs,” ACM International Conference Proceeding Series, pp. 13–16, 2012. View at Publisher · View at Google Scholar
  • Freek Verbeek, and Julien Schmaltz, “Towards the formal verification of cache coherency at the architectural level,” ACM Transactions on Design Automation of Electronic Systems, vol. 17, no. 3, 2012. View at Publisher · View at Google Scholar
  • Angelo Kuti Lusala, and Jean-Didier Legat, “A SDM-TDM-based circuit-switched router for on-chip networks,” ACM Transactions on Reconfigurable Technology and Systems, vol. 5, no. 3, 2012. View at Publisher · View at Google Scholar
  • Giuseppe Alì, Giovanni Mascali, Vittorio Romano, and Rosa Claudia Torcasio, “A Hydrodynamic Model for Covalent Semiconductors with Applications to GaN and SiC,” Acta Applicandae Mathematicae, 2012. View at Publisher · View at Google Scholar
  • Emmanouil Detsis, Yuval Brodsky, Peter Knudtson, Manuel Cuba, Heidi Fuqua, and Bianca Szalai, “Project Catch: A space based solution to combat illegal, unreported and unregulated fishing: Part I: Vessel monitoring system,” Acta Astronautica, vol. 80, pp. 114–123, 2012. View at Publisher · View at Google Scholar
  • Daniel Nies, Birgit Rehmer, Birgit Skrotzki, and Robert Vaßen, “Damage Characterization of Thermal Barrier Coatings by Acoustic Emission and Thermography,” Advanced Engineering Materials, vol. 14, no. 9, pp. 790–794, 2012. View at Publisher · View at Google Scholar
  • Oscar Montiel-Ross, Jorge Quiñones, and Roberto Sepúlveda, “Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors,” Advances in Fuzzy Systems, vol. 2012, pp. 1–11, 2012. View at Publisher · View at Google Scholar
  • Onur Derin, Prasanth Kuncheerath Ramankutty, Paolo Meloni, and Emanuele Cannella, “Towards Self-Adaptive KPN Applications on NoC-Based MPSoCs,” Advances in Software Engineering, vol. 2012, pp. 1–16, 2012. View at Publisher · View at Google Scholar
  • Gh.R. Karimi, and S. Babaei Sedaghat, “Ultra low voltage, ultra low power low noise amplifier for 2GHz applications,” AEU - International Journal of Electronics and Communications, vol. 66, no. 1, pp. 18–22, 2012. View at Publisher · View at Google Scholar
  • Gracieli Posser, Guilherme Flach, Gustavo Wilke, and Ricardo Reis, “Gate sizing using geometric programming,” Analog Integrated Circuits and Signal Processing, vol. 73, no. 3, pp. 831–840, 2012. View at Publisher · View at Google Scholar
  • Francesco Centurelli, Andrea Simonetti, and Alessandro Trifiletti, “An improved common-mode feedback loop for the differential-difference amplifier,” Analog Integrated Circuits and Signal Processing, vol. 74, no. 1, pp. 33–48, 2012. View at Publisher · View at Google Scholar
  • Martin L. R. Fürst, and Max Lein, “Semi- and Non-Relativistic Limit of the Dirac Dynamics with External Fields,” Annales Henri Poincaré, 2012. View at Publisher · View at Google Scholar
  • N. Izeboudjen, C. Larbes, and A. Farah, “A new classification approach for neural networks hardware: from standards chips to embedded systems on chip,” Artificial Intelligence Review, vol. 41, no. 4, pp. 491–534, 2012. View at Publisher · View at Google Scholar
  • Biswajit Sahu, Swarup Poria, and Rajkumar Roychoudhury, “Solitonic, quasi-periodic and periodic pattern of electron acoustic waves in quantum plasma,” Astrophysics and Space Science, vol. 341, no. 2, pp. 567–572, 2012. View at Publisher · View at Google Scholar
  • Biswajit Sahu, and Naba Kumar Ghosh, “Kadomstev-Petviashvili solitons in quantum plasmas,” Astrophysics and Space Science, vol. 343, no. 1, pp. 289–292, 2012. View at Publisher · View at Google Scholar
  • V. N. Yarmolik, “Controlled random tests,” Automation and Remote Control, vol. 73, no. 10, pp. 1704–1714, 2012. View at Publisher · View at Google Scholar
  • Johannes Partzsch, and René Schüffny, “Developing structural constraints on connectivity for biologically embedded neural networks,” Biological Cybernetics, vol. 106, no. 3, pp. 191–200, 2012. View at Publisher · View at Google Scholar
  • Christopher Maffeo, Swati Bhattacharya, Jejoong Yoo, David Wells, and Aleksei Aksimentiev, “Modeling and Simulation of Ion Channels,” Chemical Reviews, vol. 112, no. 12, pp. 6250–6284, 2012. View at Publisher · View at Google Scholar
  • John J. Kasianowicz, “Introduction to Ion Channels and Disease,” Chemical Reviews, vol. 112, no. 12, pp. 6215–6217, 2012. View at Publisher · View at Google Scholar
  • Akash Rathee, and Harish Parthasarathy, “Perturbation-Based Fourier Series Analysis of Transistor Amplifier,” Circuits Systems and Signal Processing, vol. 31, no. 1, pp. 313–328, 2012. View at Publisher · View at Google Scholar
  • Mohammad Hossein Moaiyeri, Keivan Navi, and Omid Hashemipour, “Design and Evaluation of CNFET-Based Quaternary Circuits,” Circuits, Systems, and Signal Processing, vol. 31, no. 5, pp. 1631–1652, 2012. View at Publisher · View at Google Scholar
  • K. Selvaraju, M. Jothi, and P. Kumaradhas, “Exploring the charge density distribution and the electrical characteristics of Oligo phenylene ethylene molecular nanowire using quantum chemical and charge density analysis,” Computational and Theoretical Chemistry, vol. 996, pp. 1–10, 2012. View at Publisher · View at Google Scholar
  • R. N. Simpson, S. P. A. Bordas, A. Asenov, and A. R. Brown, “Enriched residual free bubbles for semiconductor device simulation,” Computational Mechanics, vol. 50, no. 1, pp. 119–133, 2012. View at Publisher · View at Google Scholar
  • Vincent Jacquemet, “An eikonal-diffusion solver and its application to the interpolation and the simulation of reentrant cardiac activations,” Computer Methods and Programs in Biomedicine, vol. 108, no. 2, pp. 548–558, 2012. View at Publisher · View at Google Scholar
  • A.E. Botha, “General R-matrix approach for integrating the multiband equation in layered semiconductor structures,” Computer Physics Communications, vol. 183, no. 1, pp. 197–202, 2012. View at Publisher · View at Google Scholar
  • Eddie Cheng, Marc J. Lipman, and László Lipták, “Matching preclusion and conditional matching preclusion for regular interconnection networks,” Discrete Applied Mathematics, vol. 160, no. 13-14, pp. 1936–1954, 2012. View at Publisher · View at Google Scholar
  • Ireneusz Mrozek, and Vyacheslav Yarmolik, “Antirandom Test Vectors for BIST in Hardware/Software Systems,” Fundamenta Informaticae, vol. 119, no. 2, pp. 163–185, 2012. View at Publisher · View at Google Scholar
  • Johann Dambeck, and Benjamin Braun, “Analytical 2D GNSS PVT solutions from a hyperbolic positioning approach,” GPS Solutions, 2012. View at Publisher · View at Google Scholar