http://www.hindawi.comThe latest articles from Hindawi Publishing Corporation© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/165673Bozena Kaminska, Marcelo Lubaszewski, and José Machado da Silva© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/437879The research in the area of microelectronic fluidic devices for biomedical applications is rapidly growing. As faults in these devices can have serious personal implications, a system is presented which includes fault tolerance with respect to the synthesized biomaterials (peptides). It can employ presence and purity detection of peptide droplets via current (charge) tests of control electrodes or impedance (phase) measurements using direct sensing electrodes near the peptide collector area. The commercial multielectrode array performs better in pure and impure detection of peptides in impedance and phase. Our two-electrode X-MEF case shows slightly poorer results. In both cases the phase is the best choice for contents detection. If there are presence or purity problems, the location is marked, and repeated peptide synthesis at another collector site is initiated.H. G. Kerkhoff, X. Zhang, F. Mailly, P. Nouet, H. Liu, and A. Richardson© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/657207This work presents a new method to estimate the nonlinearity characteristics of analog-to-digital converters (ADCs). The method is based on a nonnecessarily polynomial continuous and differentiable mathematical model of the converter transfer function, and on the spectral processing of the converter output under a sinusoidal input excitation. The simulation and experiments performed on different ADC examples prove the feasibility of the proposed method, even when the ADC nonlinearity pattern has very strong discontinuities. When compared with the traditional code histogram method, it also shows its low cost and efficiency since a significant lower number of output samples can be used still giving very realistic INL signature values.E. J. Peralías, M. A. Jalón, and A. Rueda© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/512746A novel approach is proposed in this paper for the implementation of 2D DWT using hybrid wave-pipelining (WP). A digital circuit may be operated at a higher frequency by using either pipelining or WP. Pipelining requires additional registers and it results in more area, power dissipation and clock routing complexity. Wave-pipelining does not have any of these disadvantages but requires complex trial and error procedure for tuning the clock period and clock skew between input and output registers. In this paper, a hybrid scheme is proposed to get the benefits of both pipelining and WP techniques. In this paper, two automation schemes are proposed for the implementation of 2D DWT using hybrid WP on both Xilinx, San Jose, CA, USA and Altera FPGAs. In the first scheme, Built-in self-test (BIST) approach is used to choose the clock skew and clock period for I/O registers between the wave-pipelined blocks. In the second approach, an on-chip soft-core processor is used to choose the clock skew and clock period. The results for the hybrid WP are compared with nonpipelined and pipelined approaches. From the implementation results, the hybrid WP scheme requires the same area but faster than the nonpipelined scheme by a factor of 1.25–1.39. The pipelined scheme is faster than the hybrid scheme by a factor of 1.15–1.39 at the cost of an increase in the number of registers by a factor of 1.78–2.73, increase in the number of LEs by a factor of 1.11–1.32 and it increases the clock routing complexity.G. Seetharaman, B. Venkataramani, and G. Lakshminarayanan© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/596146With the growing complexity of wireless systems on chip integrating hundreds-of-millions of transistors, electronic design methods need to be upgraded to reduce time-to-market. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are optimized and reused for production testing. Although the original validation test set allows the verification of both design functionalities and performances, this test set is not well adapted to manufacturing test due to its high execution time and high test equipment costs requirement. The optimization of this validation test set is based on the evaluation of each test vector. This evaluation relies on high-level fault modeling and fault simulation. Hence, a fault model based on the variations of the parameters of high abstraction level descriptions and its related qualification metric are presented. The choice of functional or behavioral abstraction levels is discussed by comparing their impact on structural fault coverage. Experiments are performed on the receiver part of a WCDMA transceiver. Results show that for this SoC, using behavioral abstraction level is justified for the generation of manufacturing test benches.Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, and Jean-Louis Carbonero© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/418165Built-In RF test is a challenging problem due to the need to measure the values of complex test specifications on-chip with the precision of external RF test equipment. BIT techniques are necessary for guiding system adaptation during field operation. Prior research has demonstrated that embedded RF sensors can generate significant information about RF circuit performance. In this paper, we propose a test methodology that enables efficient BIT and BIT-enabled tuning of RF systems. A test generation approach is developed that co-optimizes the applied test stimulus, the type of embedded sensors, and the system response capture mechanisms for maximal accuracy of the BIT procedure. This BIT technique is also used to perform diagnostic testing of the transmitter. The information gathered from diagnosis is used to tune the transmitter for improved performance. Simulation results demonstrate that BIT-assisted diagnosis and tuning can be performed with good accuracy using the proposed methodology.Vishwanath Natarajan, Rajarajan Senguttuvan, Shreyas Sen, and Abhjit Chatterjee© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/912536The 402–405 MHz medical implant communication service (MICS) band has recently been allocated by the US Federal Communication Commission (FCC) with the potential to replace the low-frequency inductive coupling techniques in implantable devices. This band was particularly chosen to provide full-integration, low-power, faster data transfer, and longer communication range. This paper investigates the design of a voltage-controlled oscillator (VCO) that will be an essential building block of such wireless implantable devices operating in the MICS service band. Three different integrated quadrature VCOs that meet the requirements of the MICS standard are designed in 0.18 μm TSMC CMOS process to propose an optimum choice. Their performances in terms of power consumption, die area, linearity, and phase noise are compared. The fabricated VCOs are a four-stage differential ring VCO, an LC tank VCO directly loaded with a poly-phase filter, and an 800 MHz LC tank VCO with a high-frequency master-slave divider. All three architectures target a VCO gain of Kvco = 15 MHz/V with 3 calibration control and 2 frequency-shift keying (FSK) control signals and are designed for 1.5 V supply voltage in a 0.18-μm standard CMOS process.Ahmet Tekin, Mehmet R. Yuce, and Wentai Liu© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/294014The test of radiofrequency (RF) integrated circuits at their ever-increasing operating frequency range requires sophisticated test equipment and is time-consuming and, therefore, very expensive. This paper introduces a new method combining low-frequency actuation signal as test stimuli and signal envelope detection applied on the RF output signal in order to provide a low-cost mean for production testing of RF MEMS switches embedded in system-in-package (SiP) devices. The proposed approach uses the principle of alternate test that replaces conventional specification-based testing procedures. The basic idea is to extract the high-frequency characteristics of the switch from the signal envelope of the response. Output parameters like “on” and “off” transition time are extracted at low frequency and used in a regression process to predict RF conventional specifications like S-parameters. The paper also provides a set of recursive estimation algorithms suitable for online testing. In this context, “on” and “off” transition time estimated from the output low-frequency envelope is used as test metrics and is concurrently updated using recursive algorithms. Validation results obtained on a capacitive RF switch model are presented.E. Simeu, H. N. Nguyen, P. Cauvet, S. Mir, L. Rufer, and R. Khereddine© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/291686We describe the use of microelectromechanical system (MEMS) switches and SiGe logic devices for both passive and active loopback testing of wide data buses at rates up to 6.4 Gbps per signal. Target applications include HyperTransport, fully buffered DIMM, and PCI Express, among others. Recently introduced MEMS devices provide >7 GHz bandwidth in a very small package (needed to handle wide buses). SiGe logic supports >7 Gbps signals when active shaping of the waveform is required. Each loopback module typically supports between 9 and 16 differential channels. Multiple cards are used to handle applications with very wide buses or multiple ports. Passive cards utilize MEMS for switching between the loopback (self-test) mode and traditional automated test equipment (ATE) source/receiver channels. Future active card designs may provide additional waveform-shaping functions, such as buffering, amplitude attenuation/modulation, deskew, delay adjustment, jitter injection, and so forth. The modular approach permits precalibration of the loopback electronics and easy reconfiguration between debug or characterization testing and high-volume production screening.D. C. Keezer, D. Minier, P. Ducharme, D. Viens, G. Flynn, and J. McKillop© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/482159Standard production test techniques for ADC require an ATE with an arbitrary waveform generator (AWG) with a resolution at least 2 bits higher than the ADC under test resolution. This requirement is a real issue for the new high-performance ADCs. This paper proposes a test solution that relaxes this constraint. The technique allows the test of ADC harmonic distortions using only low-cost ATE. The method involves two steps. The first step, called the learning phase, consists in extracting the harmonic contributions from the AWG. These characteristics are then used during the second step, called the production test, to discriminate the harmonic distortions induced by the ADC under test from the ones created by the generator. Hardware experimentations are presented to validate the proposed approach.V. Kerzérho, P. Cauvet, S. Bernard, F. Azaïs, M. Renovell, M. Comte, and O. Chakib© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/892370We propose a time-consistent video segmentation algorithm designed for real-time implementation. Our algorithm is based on a region merging process that combines both spatial and motion information. The spatial segmentation takes benefit of an adaptive decision rule and a specific order of merging. Our method has proven to be efficient for the segmentation of natural images with few parameters to be set. Temporal consistency of the segmentation is ensured by incorporating motion information through the use of an improved change-detection mask. This mask is designed using both illumination differences between frames and region segmentation of the previous frame. By considering both pixel and region levels, we obtain a particularly efficient algorithm at a low computational cost, allowing its implementation in real-time on the TriMedia processor for CIF image sequences.M. El Hassani, S. Jehan-Besson, L. Brun, M. Revenu, M. Duranton, D. Tschumperlé, and D. Rivasseau© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/629076Jean-Baptiste Begueret and Thierry Taris© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/890410This paper presents a low power and high speed architecture for motion estimation with Candidate Block and Pixel Subsampling (CBPS) Algorithm. Coarse-to-fine search approach is employed to find the motion vector so that the local minima problem is totally eliminated. Pixel subsampling is performed in the selected candidate blocks which significantly reduces computational cost with low quality degradation. The architecture developed is a fully pipelined parallel design with 9 processing elements. Two different methods are deployed to reduce the power consumption, parallel and pipelined implementation and parallel accessing to memory. For processing 30 CIF frames per second our architecture requires a clock frequency of 4.5 MHz.Reeba Korah and J.Raja Paul Perinbam© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/738983This study presents a novel design approach combining wave pipelining and self reset logic, which provides an elegant solution at high-speed data throughput with significant savings in power and area as compared with other dynamic CMOS logic implementations. To overcome some limitations in SRL art, we employ a new SRL family, namely, dual-rail self reset logic with input disable (DRSRL-ID). These gates depict fairly constant timing parameters, specially the width of the output pulse, for varying fan-out and logic depth, helping accommodate process, supply voltage, and temperature variations (PVT). These properties simplify the implementation of wave pipelined circuits. General timing analysis is provided and compared with previous implementations. Results of circuit implementation are presented together with conclusions and future work.Miguel E. Litvin and Samiha Mourad© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/283451A test technique for capacitive MEMS accelerometers and electrostatic microactuators, based on the measurement of pull-in voltages and resonance frequency, is described. Using this combination of measurements, one can estimate process-induced variations in the device layout dimensions as well as deviations from nominal value in material properties, which can be used either for testing or device diagnostics purposes. Measurements performed on fabricated devices confirm that the 250 nm overetch observed on SEM images can be correctly estimated using the proposed technique.L. A. Rocha, L. Mol, E. Cretu, R. F. Wolffenbuttel, and J. Machado da Silva© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/218565The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25 μm CMOS technology at 3.3 V. The critical delay for the proposed adder is 3.4 nanoseconds. The simulation results show that the proposed adder is 18% faster than the current fastest carry-skip adder.Yu Shen Lin and Damu Radhakrishnan© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/674259The content-based access of CAMs makes them of great interest in lookup-based operations. However, the large amounts of parallel comparisons required cause an expensive cost in power dissipation. In this work, we present a novel banked precomputation-based architecture for low-power and storage-demanding applications where the reduction of both dynamic and leakage power consumption is addressed. Experimental results show that the proposed banked architecture reduces up to an 89% of dynamic power consumption during the search process while the leakage power consumption is also minimized up to a 91%.Pedro Echeverría, José L. Ayala, and Marisa López-Vallejo© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/610420This paper presents the design and implementation of a 2K/4K/8K multiple mode FFT core for DVB-T/DVB-H receivers. The proposed core is based on a pipeline radix-22 SDF architecture. The necessary changes in the radix-22 SDF architecture to achieve an efficient FFT implementation are detailed. Quantization effects and timing design parameters are analyzed for DVB-T/DVB-H. Area and power results are provided for the proposed core.A. Cortés, I. Vélez, I. Zalbide, A. Irizar, and J. F. Sevillano© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/630951In previous works of these authors, a technique for doing single-fault diagnosis in linear analog circuits was developed. Under certain conditions, one of them assuming nominal values for the circuit parameters, it was shown that only two measurements taken on two selected circuit nodes, at a single frequency, were needed to detect and diagnose any parametric fault. In this paper, the practical value of the technique is improved by extending the application to the diagnosis of faults in circuits with parameters subject to tolerance. With this in mind, single parametric faults with several strengths are randomly injected in the circuit under study and, afterwards, these faults are diagnosed (or the diagnosis fails). Results are reported on a simple active filter. Conclusions are drawn about the robustness and effectiveness of the technique.José A. Soares Augusto and Carlos Beltrán Almeida© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/351962Multi-input multi-output (MIMO) systems combined with orthogonal frequency-division multiplexing (OFDM) gained a wide popularity in wireless applications due to the potential of providing increased channel capacity and robustness against multipath fading channels. However these advantages come at the cost of a very high processing complexity and the efficient implementation of MIMO-OFDM receivers is today a major research topic. In this paper, efficient architectures are proposed for the hardware implementation of the main building blocks of a MIMO-OFDM receiver. A sphere decoder architecture flexible to different modulation without any loss in BER performance is presented while the proposed matrix factorization implementation allows to achieve the highest throughput specified in the IEEE 802.11n standard. Finally a novel E8 sphere decoder approach is presented, which allows for the realization of new golden space time trellis coded modulation (GST-TCM) scheme. Implementation cost and offered throughput are provided for the proposed architectures synthesized on a 0.13 μm CMOS standard cell technology or on advanced FPGA devices.Barbara Cerato, Guido Masera, and Emanuele Viterbo© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/160728We present an IP-core called PHCA which stands for programmable hardware cellular automaton. PHCA is a hardware implementation of a general purpose cellular automaton (CA) entirely programmable. The heart of this structure is a PE array with reconfigurable side links allowing the implementation of a 2D CA or a 1D CA. As an illustration of a PHCA program, we present the implementation of a symmetric cryptography algorithm called ISEA for Ising spin encryption algorithm. Indeed ISEA is based on a 2D Ising spin lattice presenting random series of disordered spin configurations. The main idea of ISEA is to use this disorder to encrypt data. Efficiency of ISEA and PHCA implementation results are given.Samuel Charbouillot, Annie Pérez, and Daniele Fronte© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/165709Random testing requires each test to be selected randomly regardless of the tests previously applied. This paper introduces the concept of antirandom testing where each test applied is chosen such that its total distance from all previous tests is maximum. This spans the test vector space to the maximum extent possible for a given number of vectors. An algorithm for generating antirandom tests is presented. Compared with traditional pseudorandom testing, antirandom testing is found to be very effective when a high-fault coverage needs to be achieved with a limited number of test vectors. The superiority of the new approach is even more significant for testing bridging faults.Shen Hui Wu, Sridhar Jandhyala, Yashwant K. Malaiya, and Anura P. Jayasumana© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/680157Test set embedding built-in self test (BIST) schemes are a class of pseudorandom BIST techniques where the test set is embedded into the sequence generated by the BIST pattern generator, and they displace common pseudorandom schemes in cases where reverse-order simulation cannot be applied. Single-seed embedding schemes embed the test set into a single sequence and demand extremely small hardware overhead since no additional control or memory to reconfigure the test pattern generator is required. The challenge in this class of schemes is to choose the best pattern generator among various candidate configurations. This, in turn, calls for a need to evaluate the location of each test pattern in the sequence as fast as possible, in order to try as many candidate configurations as possible for the test pattern generator. This problem is known as the test vector-embedding problem. In this paper we present a novel solution to the test vector-embedding problem for sequences generated by accumulators. The time overhead of the solution is of the order O(1). The applicability of the presented method for embedding test sets for the testing of real-world circuits is investigated through experimental results in some well-known benchmarks; comparisons with previously proposed schemes indicate that comparable test lengths are achieved, while the time required for the calculations is accelerated by more than 30 times.Ioannis Voyiatzis© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/479173A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA) has been designed using Silterra's industry standard 0.18 μm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA). A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of −17.8 dB, S22 of −10.7 dB, and input 1 dB compression point of −12 dBm at 3 GHzLer Chun Lee, Abu Khari bin A'ain, and Albert Victor Kordesch© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/847932A new methodology based on the concept of figure of merit under area constraints is described for designing optimum performance differential amplifiers. First a figure of merit is introduced that includes the three performance parameters, namely, input-referred noise, differential dc gain, and unity-gain bandwidth. Expressions for these parameters have been derived analytically and finally arrived at an expression for the figure of merit. Next it is shown how these performance parameters vary with the relative allocation of the total available area between the input and load transistors. The figure of merit peaks at a certain value of relative area allocation in the range of 60% to 80% of the available area to the input transistors. The peak value of figure of merit is a function of area. However, it is independent of biasing current (and, therefore, power consumption) subject to the minimum current (and, therefore, a minimum power) required to keep all the transistors biased in the saturation region. The peak figure of merit and minimum power required to achieve the peak figure of merit are also plotted as a function of area. These analyses help in synthesizing optimal differential amplifier circuit designs under area constraints.Alpana Agarwal and Chandra Shekhar© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/753043This paper presents an FPGA implementation of a high-performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance. By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.Péter Szántó, Gábor Szedő, and Béla Fehér© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/312614Future 4th Generation (4G) wireless multiuser communication systems will have to provide advanced multimedia services to an increasing number of users, making good use of the scarce spectrum resources. Thus, 4G system design should pursue both higher-transmission bit rates and higher spectral efficiencies. To achieve this goal, multiple antenna systems are called to play a crucial role. In this contribution we address the implementation in FPGAs of a multiple-input multiple-output (MIMO) decoder embedded in a prototype of a 4G mobile receiver. This MIMO decoder is part of a multicarrier code-division multiple-access (MC-CDMA) radio system, equipped with multiple antennas at both ends of the link, that is able to handle up to 32 users and provides raw transmission bit-rates up to 125 Mbps. The task of the MIMO decoder is to appropriately combine the signals simultaneously received on all antennas to construct an improved signal, free of interference, from which to estimate the transmitted symbols. A comprehensive explanation of the complete design process is provided, including architectural decisions, floating-point to fixed-point translation, and description of the validation procedure. We also report implementation results using FPGA devices of the Xilinx Virtex-4 family.Alberto Jiménez-Pacheco, Ángel Fernández-Herrero, and Javier Casajús-Quirós© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2007/58431This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.Zheng Shen, Hu He, Yanjun Zhang, and Yihe Sun© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2007/67019The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, a row bank-based precharge technique based on the divided wordline (DWL) architecture is proposed for low-power testing of embedded SRAMs. The memory cell array is first divided into row banks. The effectiveness of the row bank-based precharge technique is due to the predictable address sequence during test. In low-power test mode, instead of precharging the entire memory array, only the current accessed row bank is precharged. This will result in significant power saving for the precharge circuitry. The precharge power can be reduced to 1/b of that of the traditional precharge techniques, where b denotes the number of row banks in the memory array. With simple transmission gates and inverters, the modified precharge control circuitry was also designed. The hardware overhead for implementing the low-power technique is almost negligible. Moreover, the corresponding BIST design to implement the low-power technique is almost the same as the conventional BIST designs. It is also notable that the inherent low-power characteristics of the DWL architecture can be preserved. According to experimental results, 48.9% power reduction can be achieved for a 256 × 256 bit-oriented SRAM. The memory is divided into 8 row banks. Moreover, if the number of row banks increases, the power saving will also increase.Shyue-Kung Lu, Yuang-Cheng Hsiao, Chia-Hsiu Liu, and Chun-Lin Yang© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2000/12198In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing diverse resource types in the new FPGA architectures. We first propose a network flow based method to optimally check whether a circuit or a subcircuit is feasible for a set of available heterogeneous resources. Then the feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementation. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple FPGA designs (e.g., logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical FPGA (e.g., Actel's ES6500 FPGA family).Huiqun Liu, Kai Zhu, and D. F. Wong© 2008, Hindawi Publishing Corporation. All rights reserved.