VLSI Design http://www.hindawi.com The latest articles from Hindawi Publishing Corporation © 2016 , Hindawi Publishing Corporation . All rights reserved. Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits Wed, 27 Apr 2016 08:54:47 +0000 http://www.hindawi.com/journals/vlsi/2016/3191286/ The increased number of complex functional units exerts high power-density within a very-large-scale integration (VLSI) chip which results in overheating. Power-densities directly converge into temperature which reduces the yield of the circuit. An adverse effect of power-density reduction is the increase in area. So, there is a trade-off between area and power-density. In this paper, we introduce a Shared Reed-Muller Decision Diagram (SRMDD) based on fixed polarity AND-XOR decomposition to represent multioutput Boolean functions. By recursively applying transformations and reductions, we obtained a compact SRMDD. A heuristic based on Genetic Algorithm (GA) increases the sharing of product terms by judicious choice of polarity of input variables in SRMDD expansion and a suitable area and power-density trade-off has been enumerated. This is the first effort ever to incorporate the power-density as a measure of temperature estimation in AND-XOR expansion process. The results of logic synthesis are incorporated with physical design in CADENCE digital synthesis tool to obtain the floor-plan silicon area and power profile. The proposed thermal-aware synthesis has been validated by obtaining absolute temperature of the synthesized circuits using HotSpot tool. We have experimented with 29 benchmark circuits. The minimized AND-XOR circuit realization shows average savings up to 15.23% improvement in silicon area and up to 17.02% improvement in temperature over the sum-of-product (SOP) based logic minimization. Apangshu Das and Sambhu Nath Pradhan Copyright © 2016 Apangshu Das and Sambhu Nath Pradhan. All rights reserved. A Novel Time Synchronization Method for Dynamic Reconfigurable Bus Sun, 03 Apr 2016 06:08:41 +0000 http://www.hindawi.com/journals/vlsi/2016/5752080/ UM-BUS is a novel dynamically reconfigurable high-speed serial bus for embedded systems. It can achieve fault tolerance by detecting the channel status in real time and reconfigure dynamically at run-time. The bus supports direct interconnections between up to eight master nodes and multiple slave nodes. In order to solve the time synchronization problem among master nodes, this paper proposes a novel time synchronization method, which can meet the requirement of time precision in UM-BUS. In this proposed method, time is firstly broadcasted through time broadcast packets. Then, the transmission delay and time deviations via three handshakes during link self-checking and channel detection can be worked out referring to the IEEE 1588 protocol. Thereby, each node calibrates its own time according to the broadcasted time. The proposed method has been proved to meet the requirement of real-time time synchronization. The experimental results show that the synchronous precision can achieve a bias less than 20 ns. Zhang Weigong, Li Chao, Qiu Keni, Zhang Shaonan, and Chen Xianglong Copyright © 2016 Zhang Weigong et al. All rights reserved. Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits Mon, 26 Oct 2015 06:16:56 +0000 http://www.hindawi.com/journals/vlsi/2015/540482/ The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. To this purpose, a GLBB mirror full adder is implemented by using a commercial 45 nm bulk CMOS triple-well technology and compared to equivalent conventional zero body-biased CMOS and dynamic threshold voltage MOSFET (DTMOS) circuits under different running conditions. Postlayout simulations demonstrate that, at the parity of leakage power consumption, the GLBB technique exhibits a significant concurrent reduction of the energy per operation and the delay in comparison to the conventional CMOS and DTMOS approaches. The silicon area required by the GLBB full adder is halved with respect to the equivalent DTMOS implementation, but it is higher in comparison to conventional CMOS design. Performed analysis also proves that the GLBB solution exhibits a high level of robustness against temperature fluctuations and process variations. Ramiro Taco, Marco Lanuzza, and Domenico Albano Copyright © 2015 Ramiro Taco et al. All rights reserved. The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach Tue, 13 Oct 2015 07:22:39 +0000 http://www.hindawi.com/journals/vlsi/2015/312639/ With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This paper describes the design of RF LNAs using a geometric programming (GP) optimization method. An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noise observed in the MOSFETs. An extensive survey of analytical models and experimental results reported in the literature is carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Short channel effects such as channel-length modulation and velocity saturation effects are also accounted for in our optimization process. The GP approach is able to efficiently calculate the globally optimum solution. The approximations required to setup the equations and constraints to allow convex optimization are detailed. The method is applied to the design of inductive source degenerated common source amplifiers at the 90 nm and 180 nm technology nodes. The optimization results are validated through comparison with numerical simulations using Agilent’s Advanced Design Systems (ADS) software. David H. K. Hoe and Xiaoyu Jin Copyright © 2015 David H. K. Hoe and Xiaoyu Jin. All rights reserved. A Modularized Noise Analysis Method with Its Application in Readout Circuit Design Wed, 09 Sep 2015 07:14:14 +0000 http://www.hindawi.com/journals/vlsi/2015/593019/ A readout integrated circuit (ROIC) is a crucial part that determines the quality of imaging. In order to analyze the noise of a ROIC with distinct illustration of each noise source transferring, a modularized noise analysis method is proposed whose application is applied for a ROIC cell, where all the MOSFETs are optimized in subthreshold region, leading to the power dissipation 2.8 μW. The modularized noise analysis begins with the noise model built using transfer functions and afterwards presents the transfer process of noise in the form of matrix, through which we can describe the contribution of each noise source to the whole output noise clearly, besides optimizing the values of key components. The optimal noise performance is obtained under the limitation of layout area less than 30 μm × 30 μm, resulting in that the integration capacitor should be selected as 0.74 pF to achieve an optimal noise performance, the whole output noise reaching the minimum value at 74.1 μV. In the end transient simulations utilizing Verilog-A are carried out for comparisons. The results showing good agreement verify the feasibility of the method presented through matrix. Xiao Wang, Zelin Shi, and Baoshu Xu Copyright © 2015 Xiao Wang et al. All rights reserved. Analysis and Implementation of Kidney Stone Detection by Reaction Diffusion Level Set Segmentation Using Xilinx System Generator on FPGA Tue, 02 Jun 2015 08:21:48 +0000 http://www.hindawi.com/journals/vlsi/2015/581961/ Ultrasound imaging is one of the available imaging techniques used for diagnosis of kidney abnormalities, which may be like change in shape and position and swelling of limb; there are also other Kidney abnormalities such as formation of stones, cysts, blockage of urine, congenital anomalies, and cancerous cells. During surgical processes it is vital to recognize the true and precise location of kidney stone. The detection of kidney stones using ultrasound imaging is a highly challenging task as they are of low contrast and contain speckle noise. This challenge is overcome by employing suitable image processing techniques. The ultrasound image is first preprocessed to get rid of speckle noise using the image restoration process. The restored image is smoothened using Gabor filter and the subsequent image is enhanced by histogram equalization. The preprocessed image is achieved with level set segmentation to detect the stone region. Segmentation process is employed twice for getting better results; first to segment kidney portion and then to segment the stone portion, respectively. In this work, the level set segmentation uses two terms, namely, momentum and resilient propagation () to detect the stone portion. After segmentation, the extracted region of the kidney stone is given to Symlets, Biorthogonal (bio3.7, bio3.9, and bio4.4), and Daubechies lifting scheme wavelet subbands to extract energy levels. These energy levels provide evidence about presence of stone, by comparing them with that of the normal energy levels. They are trained by multilayer perceptron (MLP) and back propagation (BP) ANN to classify and its type of stone with an accuracy of 98.8%. The prosed work is designed and real time is implemented on both Filed Programmable Gate Array Vertex-2Pro FPGA using Xilinx System Generator (XSG) Verilog and Matlab 2012a. Kalannagari Viswanath and Ramalingam Gunasundari Copyright © 2015 Kalannagari Viswanath and Ramalingam Gunasundari. All rights reserved. Functional Testbench Qualification by Mutation Analysis Thu, 07 May 2015 13:40:07 +0000 http://www.hindawi.com/journals/vlsi/2015/256474/ The growing complexity and higher time-to-market pressure make the functional verification of modern large scale hardware systems more challenging. These challenges bring the requirement of a high quality testbench that is capable of thoroughly verifying the design. To reveal a bug, the testbench needs to activate it by stimulus, propagate the erroneous behaviors to some checked points, and detect it at these checked points by checkers. However, current dominant verification approaches focus only on the activation aspect using a coverage model which is not qualified and ignore the propagation and detection aspects. Using a new metric, this paper qualifies the testbench by mutation analysis technique with the consideration of the quality of the stimulus, the coverage model, and the checkers. Then the testbench is iteratively refined according to the qualification feedback. We have conducted experiments on two designs of different scales to demonstrate the effectiveness of the proposed method in improving the quality of the testbench. Kai Huang, Peng Zhu, Rongjie Yan, and Xiaolang Yan Copyright © 2015 Kai Huang et al. All rights reserved. A Discrete Event System Approach to Online Testing of Speed Independent Circuits Thu, 30 Apr 2015 13:00:27 +0000 http://www.hindawi.com/journals/vlsi/2015/651785/ With the increase in soft failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of a checker that verifies the correctness of the protocol. This checker involves Mutex blocks making its area overhead quite high. In this paper, we have adapted the Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems to online testing of speed independent asynchronous circuits. The scheme involves development of a state based model of the circuit, under normal and various stuck-at fault conditions, and finally designing state estimators termed as detectors. The detectors monitor the circuit online and determine whether it is functioning in normal/failure mode. The main advantages are nonintrusiveness and low area overheads compared to similar schemes reported in the literature. P. K. Biswal, K. Mishra, S. Biswas, and H. K. Kapoor Copyright © 2015 P. K. Biswal et al. All rights reserved. A Novel Scan Architecture for Low Power Scan-Based Testing Wed, 22 Apr 2015 07:45:40 +0000 http://www.hindawi.com/journals/vlsi/2015/264071/ Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17% total average power compared to conventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures. Mahshid Mojtabavi Naeini and Chia Yee Ooi Copyright © 2015 Mahshid Mojtabavi Naeini and Chia Yee Ooi. All rights reserved. Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection Wed, 15 Apr 2015 11:56:34 +0000 http://www.hindawi.com/journals/vlsi/2015/408035/ A wide tuning band pass filter (BPF) with steep roll-off high rejection and low noise figure is presented. The design feature of steep roll-off high stopband rejection (>20 dB) and low noise figure (<6 dB) provides a wide tuning frequency span (1–2.04 GHz) to accept desirable signals and reject close interfering signals. The process variation aware design approach demonstrates robustness of the BPF after calibration from process variations, operating in 1.04 GHz tuning frequency span: almost zero deviation on center frequency, an average maximum deviation 1.16 dB on a nominal pass band gain of 55.6 dB, and an average maximum deviation 1.06 MHz on a nominal bandwidth of 12.3 MHz. Jian Chen and Chien-In Henry Chen Copyright © 2015 Jian Chen and Chien-In Henry Chen. All rights reserved. A New CDS Structure for High Density FPA with Low Power Sun, 01 Feb 2015 12:50:22 +0000 http://www.hindawi.com/journals/vlsi/2015/767161/ Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing. Xiao Wang and Zelin Shi Copyright © 2015 Xiao Wang and Zelin Shi. All rights reserved. Advanced VLSI Architecture Design for Emerging Digital Systems Mon, 22 Dec 2014 09:55:38 +0000 http://www.hindawi.com/journals/vlsi/2014/746132/ Yu-Cheng Fan, Qiaoyan Yu, Thomas Schumann, Ying-Ren Chien, and Chih-Cheng Lu Copyright © 2014 Yu-Cheng Fan et al. All rights reserved. Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics Thu, 18 Dec 2014 00:10:21 +0000 http://www.hindawi.com/journals/vlsi/2014/493189/ Complexity in processor microarchitecture and the related issues of power density, hot spots and wire delay, are seen to be a major concern for design migration into low nanometer technologies of the future. This paper evaluates the hardware cost of an alternative to register-file organization, the superscalar stack issue array (SSIA). We believe this is the first such reported study using discrete stack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding delay data and FO4 metrics. The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a 4-wide issue rate of at least four Giga-ops/sec at 90 nm and opportunities for twofold future improvement by using more advanced design approaches. Christopher Bailey and Brendan Mullane Copyright © 2014 Christopher Bailey and Brendan Mullane. All rights reserved. On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing Sun, 16 Nov 2014 00:00:00 +0000 http://www.hindawi.com/journals/vlsi/2014/465907/ We propose an approach to design of an algebraic signature analyzer that can be used for mixed-signal systems testing. The analyzer does not contain carry propagating circuitry, which improves its performance as well as fault tolerance. The common design technique of a signature analyzer for mixed-signal systems is based on the rules of an arithmetic finite field. The application of this technique to the systems with an arbitrary radix is a challenging task and the devices designed possess high hardware complexity. The proposed technique is simple and applicable to systems of any size and radix. The hardware complexity is low. The technique can also be used in arithmetic/algebraic coding and cryptography. Vadim Geurkov and Lev Kirischian Copyright © 2014 Vadim Geurkov and Lev Kirischian. All rights reserved. High-Efficient Circuits for Ternary Addition Mon, 01 Sep 2014 05:09:51 +0000 http://www.hindawi.com/journals/vlsi/2014/534587/ New ternary adders, which are fundamental components of ternary addition, are presented in this paper. They are on the basis of a logic style which mostly generates binary signals. Therefore, static power dissipation reaches its minimum extent. Extensive different analyses are carried out to examine how efficient the new designs are. For instance, the ternary ripple adder constructed by the proposed ternary half and full adders consumes 2.33 μW less power than the one implemented by the previous adder cells. It is almost twice faster as well. Due to their unique superior characteristics for ternary circuitry, carbon nanotube field-effect transistors are used to form the novel circuits, which are entirely suitable for practical applications. Reza Faghih Mirzaee, Keivan Navi, and Nader Bagherzadeh Copyright © 2014 Reza Faghih Mirzaee et al. All rights reserved. Engineering Change Orders Design Using Multiple Variables Linear Programming for VLSI Design Sun, 24 Aug 2014 11:40:10 +0000 http://www.hindawi.com/journals/vlsi/2014/698041/ An engineering change orders design using multiple variable linear programming for VLSI design is presented in this paper. This approach addresses the main issues of resource between spare cells and target cells. We adopt linear programming technique to plan and balance the spare cells and target cells to meet the new specification according to logic transformation. The proposed method solves the related problem of resource for ECO problems and provides a well solution. The scheme shows new concept to manage the spare cells to meet possible target cells for ECO research. Yu-Cheng Fan, Chih-Kang Lin, Shih-Ying Chou, Chun-Hung Wang, Shu-Hsien Wu, and Hung-Kuan Liu Copyright © 2014 Yu-Cheng Fan et al. All rights reserved. Design of Smart Power-Saving Architecture for Network on Chip Wed, 06 Aug 2014 11:22:49 +0000 http://www.hindawi.com/journals/vlsi/2014/531653/ In network-on-chip (NoC), the data transferring by virtual channels can avoid the issue of data loss and deadlock. Many virtual channels on one input or output port in router are included. However, the router includes five I/O ports, and then the power issue is very important in virtual channels. In this paper, a novel architecture, namely, Smart Power-Saving (SPS), for low power consumption and low area in virtual channels of NoC is proposed. The SPS architecture can accord different environmental factors to dynamically save power and optimization area in NoC. Comparison with related works, the new proposed method reduces 37.31%, 45.79%, and 19.26% on power consumption and reduces 49.4%, 25.5% and 14.4% on area, respectively. Trong-Yen Lee and Chi-Han Huang Copyright © 2014 Trong-Yen Lee and Chi-Han Huang. All rights reserved. Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool Thu, 24 Jul 2014 11:25:02 +0000 http://www.hindawi.com/journals/vlsi/2014/280701/ Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power. Deepa Yagain and A. Vijaya Krishna Copyright © 2014 Deepa Yagain and A. Vijaya Krishna. All rights reserved. Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design Wed, 23 Jul 2014 07:26:22 +0000 http://www.hindawi.com/journals/vlsi/2014/406416/ We are going to design and simulate low power fractional-N phase-locked loop (FNPLL) frequency synthesizer for industrial application, which is based on VLSI. The design of FNPLL has been optimized using different VLSI techniques to acquire significant performance in terms of speed with relatively less power consumption. One of the major contributions in optimization is contributed by the loop filter as it limits the switching time between cycles. Sigma-delta modulator attenuates the noise generated by the loop filter. This paper presents the implementation details and simulation results of all the blocks of optimized design. Sahar Arshad, Muhammad Ismail, Usman Ahmad, Anees ul Husnain, and Qaiser Ijaz Copyright © 2014 Sahar Arshad et al. All rights reserved. Parallel Jacobi EVD Methods on Integrated Circuits Sun, 20 Jul 2014 11:52:53 +0000 http://www.hindawi.com/journals/vlsi/2014/596103/ Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design criteria for integrated circuits, A 10 × 10 Jacobi Brent-Luk-EVD array with the simplified μ-CORDIC processor is used as an example. The experimental results show that using the μ-CORDIC processor is beneficial for the design criteria as it yields a smaller area, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that the proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing beamforming or DOA estimation. Chi-Chia Sun, Jürgen Götze, and Gene Eu Jan Copyright © 2014 Chi-Chia Sun et al. All rights reserved. Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits Tue, 15 Jul 2014 08:26:36 +0000 http://www.hindawi.com/journals/vlsi/2014/380362/ This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption. Shikha Panwar, Mayuresh Piske, and Aatreya Vivek Madgula Copyright © 2014 Shikha Panwar et al. All rights reserved. Gate-Level Circuit Reliability Analysis: A Survey Thu, 10 Jul 2014 09:58:59 +0000 http://www.hindawi.com/journals/vlsi/2014/529392/ Circuit reliability has become a growing concern in today’s nanoelectronics, which motivates strong research interest over the years in reliability analysis and reliability-oriented circuit design. While quite a few approaches for circuit reliability analysis have been reported, there is a lack of comparative studies on their pros and cons in terms of both accuracy and efficiency. This paper provides an overview of some typical methods for reliability analysis with focus on gate-level circuits, large or small, with or without reconvergent fanouts. It is intended to help the readers gain an insight into the reliability issues, and their complexity as well as optional solutions. Understanding the reliability analysis is also a first step towards advanced circuit designs for improved reliability in the future research. Ran Xiao and Chunhong Chen Copyright © 2014 Ran Xiao and Chunhong Chen. All rights reserved. High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos Mon, 07 Jul 2014 11:19:19 +0000 http://www.hindawi.com/journals/vlsi/2014/923618/ This paper presents a new multioutput and high throughput pseudorandom number generator. The scheme is to make the homogenized Logistic chaotic sequence as unified hyperchaotic system parameter. So the unified hyperchaos can transfer in different chaotic systems and the output can be more complex with the changing of homogenized Logistic chaotic output. Through processing the unified hyperchaotic 4-way outputs, the output will be extended to 26 channels. In addition, the generated pseudorandom sequences have all passed NIST SP800-22 standard test and DIEHARD test. The system is designed in Verilog HDL and experimentally verified on a Xilinx Spartan 6 FPGA for a maximum throughput of 16.91 Gbits/s for the native chaotic output and 13.49 Gbits/s for the resulting pseudorandom number generators. Kaiyu Wang, Qingxin Yan, Shihua Yu, Xianwei Qi, Yudi Zhou, and Zhenan Tang Copyright © 2014 Kaiyu Wang et al. All rights reserved. Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity Thu, 05 Jun 2014 09:05:16 +0000 http://www.hindawi.com/journals/vlsi/2014/825183/ Physical control format indicator channel (PCFICH) carries the control information about the number of orthogonal frequency division multiplexing (OFDM) symbols used for transmission of control information in long term evolution-advanced (LTE-A) downlink system. In this paper, two novel low complexity receiver architectures are proposed to implement the maximum likelihood- (ML-) based algorithm which decodes the CFI value in field programmable gate array (FPGA) at user equipment (UE). The performance of the proposed architectures is analyzed in terms of the timing cycles, operational resource requirement, and resource complexity. In LTE-A, base station and UE have multiple antenna ports to provide transmit and receive diversities. The proposed architectures are implemented in Virtex-6 xc6vlx240tff1156-1 FPGA device for various antenna configurations at base station and UE. When multiple antenna ports are used at base station, transmit diversity is obtained by applying the concept of space frequency block code (SFBC). It is shown that the proposed architectures use minimum number of operational units in FPGA compared to the traditional direct method of implementation. S. Syed Ameer Abbas, S. J. Thiruvengadam, and S. Susithra Copyright © 2014 S. Syed Ameer Abbas et al. All rights reserved. VLSI Architectures for Image Interpolation: A Survey Mon, 19 May 2014 00:00:00 +0000 http://www.hindawi.com/journals/vlsi/2014/872501/ Image interpolation is a method of estimating the values at unknown points using the known data points. This procedure is used in expanding and contrasting digital images. In this survey, different types of interpolation algorithm and their hardware architecture have been analyzed and compared. They are bilinear, winscale, bi-cubic, linear convolution, extended linear, piecewise linear, adaptive bilinear, first order polynomial, and edge enhanced interpolation architectures. The algorithms are implemented for different types of field programmable gate array (FPGA) and/or by different types of complementary metal oxide semiconductor (CMOS) technologies like TSMC 0.18 and TSMC 0.13. These interpolation algorithms are compared based on different types of optimization such as gate count, frequency, power, and memory buffer. The goal of this work is to analyze the different very large scale integration (VLSI) parameters like area, speed, and power of various implementations for image interpolation. From the survey followed by analysis, it is observed that the performance of hardware architecture of image interpolation can be improved by minimising number of line buffer memory and removing superfluous arithmetic elements on generating weighting coefficient. C. John Moses, D. Selvathi, and V. M. Anne Sophia Copyright © 2014 C. John Moses et al. All rights reserved. Radix-2α/4β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation Tue, 13 May 2014 11:25:36 +0000 http://www.hindawi.com/journals/vlsi/2014/690594/ This paper describes an embedded FFT processor where the higher radices butterflies maintain one complex multiplier in its critical path. Based on the concept of a radix-r fast Fourier factorization and based on the FFT parallel processing, we introduce a new concept of a radix-r Fast Fourier Transform in which the concept of the radix-r butterfly computation has been formulated as the combination of radix-2α/4β butterflies implemented in parallel. By doing so, the VLSI butterfly implementation for higher radices would be feasible since it maintains approximately the same complexity of the radix-2/4 butterfly which is obtained by block building of the radix-2/4 modules. The block building process is achieved by duplicating the block circuit diagram of the radix-2/4 module that is materialized by means of a feed-back network which will reuse the block circuit diagram of the radix-2/4 module. Marwan A. Jaber and Daniel Massicotte Copyright © 2014 Marwan A. Jaber and Daniel Massicotte. All rights reserved. Low-Area Wallace Multiplier Mon, 12 May 2014 11:29:08 +0000 http://www.hindawi.com/journals/vlsi/2014/343960/ Multiplication is one of the most commonly used operations in the arithmetic. Multipliers based on Wallace reduction tree provide an area-efficient strategy for high speed multiplication. A number of modifications are proposed in the literature to optimize the area of the Wallace multiplier. This paper proposed a reduced-area Wallace multiplier without compromising on the speed of the original Wallace multiplier. Designs are synthesized using Synopsys Design Compiler in 90 nm process technology. Synthesis results show that the proposed multiplier has the lowest area as compared to other tree-based multipliers. The speed of the proposed and reference multipliers is almost the same. Shahzad Asif and Yinan Kong Copyright © 2014 Shahzad Asif and Yinan Kong. All rights reserved. Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic Sun, 11 May 2014 12:04:54 +0000 http://www.hindawi.com/journals/vlsi/2014/652187/ Offshore fabrication, assembling and packaging challenge chip security, as original chip designs may be tampered by malicious insertions, known as hardware Trojans (HTs). HT detection is imperative to guarantee the chip performance and safety. Existing HT detection methods have limited capability to detect small-scale HTs and are further challenged by the increased process variation. To increase HT detection sensitivity and reduce chip authorization time, we propose to exploit the inherent feature of differential cascade voltage switch logic (DCVSL) to detect HTs at runtime. In normal operation, a system implemented with DCVSL always produces complementary logic values in internal nets and final outputs. Noncomplementary values on inputs and internal nets in DCVSL systems potentially result in abnormal power behavior and even system failures. By examining special power characteristics of DCVSL systems upon HT insertion, we can detect HTs, even if the HT size is small. Simulation results show that the proposed method achieves up to 100% HT detection rate. The evaluation on ISCAS benchmark circuits shows that the proposed method obtains a HT detection rate in the range of 66% to 98%. Wafi Danesh, Jaya Dofe, and Qiaoyan Yu Copyright © 2014 Wafi Danesh et al. All rights reserved. On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding Tue, 06 May 2014 07:38:43 +0000 http://www.hindawi.com/journals/vlsi/2014/801241/ In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor core, resulting in a high volume of diverse data transfer through the L1-L2 cache bus. High-performance CMP and SoC systems have a significant amount of data transfer between the on-chip L2 cache and the L3 cache of off-chip memory through the power expensive off-chip memory bus. This paper addresses the problem of the high-power consumption of the on-chip data buses, exploring a framework for memory data bus power consumption minimization approach. A comprehensive analysis of the existing bus power minimization approaches is provided based on the performance, power, and area overhead consideration. A novel approaches for reducing the power consumption for the on-chip bus is introduced. In particular, a serialization-widening (SW) of data bus with frequent value encoding (FVE), called the SWE approach, is proposed as the best power savings approach for the on-chip cache data bus. The experimental results show that the SWE approach with FVE can achieve approximately 54% power savings over the conventional bus for multicore applications using a 64-bit wide data bus in 45 nm technology. Khader Mohammad, Ahsan Kabeer, and Tarek Taha Copyright © 2014 Khader Mohammad et al. All rights reserved. A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients Sun, 04 May 2014 12:01:55 +0000 http://www.hindawi.com/journals/vlsi/2014/651943/ We introduce a dynamically reconfigurable 2D filterbank that supports both real and complex-valued inputs, outputs, and filter coefficients. This general purpose filterbank allows for the efficient implementation of 2D filterbanks based on separable 2D FIR filters that support all possible combinations of input and output signals. The system relies on the use of dynamic reconfiguration of real/complex one-dimensional filters to minimize the required hardware resources. The system is demonstrated using an equiripple and a Gabor filterbank and the results using both real and complex-valued input images. We summarize the performance of the system in terms of the required processing times, energy, and accuracy. Daniel Llamocca and Marios Pattichis Copyright © 2014 Daniel Llamocca and Marios Pattichis. All rights reserved.