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VLSI Testing
Guest Editor: Sunil Das- Guest Editorial, Sunil R. Das
Volume 4 (1996), Issue 3, Pages i-iv - PGEN: A Novel Approach to Sequential Circuit Test Generation, Wen-Ben Jone, Nigam Shah, Anita Gleason, and Sunil R. Das
Volume 4 (1996), Issue 3, Pages 149-165 - A Novel Path Delay Fault Simulator Using Binary Logic, Ananta K. Majhi, James Jacob, and Lalit M. Patnaik
Volume 4 (1996), Issue 3, Pages 167-179 - HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits, Kyuchull Kim and Kewal K. Saluja
Volume 4 (1996), Issue 3, Pages 181-197 - Closed Form Aliasing Probability For Q-ary Symmetric Errors, Geetani Edirisooriya
Volume 4 (1996), Issue 3, Pages 199-205 - On Generating Optimal Signal Probabilities for Random Tests: A Genetic Approach, M. Srinivas and L. M. Patnaik
Volume 4 (1996), Issue 3, Pages 207-215 - Switch-level Differential Fault Simulation of MOS VLSI Circuits, Evstratios Vandris and Gerald Sobelman
Volume 4 (1996), Issue 3, Pages 217-229 - Fault Modeling of ECL for High Fault Coverage of Physical Defects, Sankaran M. Menon, Yashwant K. Malaiya, and Anura P. Jayasumana
Volume 4 (1996), Issue 3, Pages 231-242 - A Modified Approach to Test Plan Generation for Combinational Logic Blocks, Anupam Basu, Dilip K. Banerji, Amit Basu, T. C. Wilson, and Jay C. Majithia
Volume 4 (1996), Issue 3, Pages 243-256 - A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays, S. Bandyopadhyay, A. Sengupta, and B. B. Bhattacharya
Volume 4 (1996), Issue 3, Pages 257-269 - Erratum
Volume 4 (1996), Issue 3, Pages 271-274