Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a widediversity of logic building blocks. Although logic designers have been building circuits for many years, they have realizedthat advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In thispaper, we present the fundamentals of a logic design methodology which meets the requirements of today&#39;s complex circuitsand modem building blocks. The methodology is based on the theory of general full-decompositions which constitutes thetheory of digital circuit structures at the highest abstraction level. The paper explains the theory and shows how it can beused for digital circuit synthesis. The decomposition methodology that is presented ensures &#8220;correctness by construction&#8221;and enables very effective and efficient post-factum validation. It makes possible extensive examination of the structuralfeatures of the required information processing in relation to a given set of objectives and constraints.

Lech  J&#243;&#378;wiak

General Decomposition and Its Use in Digital Circuit Synthesis

Here we present a new method for the decomposition of a Finite State Machine (FSM) into a network of interacting FSMsand a framework for the functional verification of the FSM network at different levels of abstraction. The problem ofdecomposition is solved by output partitioning and state space decomposition using a multiway graph partitioningtechnique. The number of submachines is determined dynamically during the partitioning process. The verificationalgorithm can be used to verify (a) the result of FSM decomposition on a behavioral level, (b) the encoded FSM network,and (c) the FSM network after logic optimization. Our verification technique is based on an efficient enumeration-simulationmethod which involves traversal of the state transition graph of the prototype machine and simulation of the decomposedmachine network. Both the decomposition and verification/simulation algorithms have been implemented as part of aninteractive FSM synthesis system and tested on a set of benchmark examples.

Zafar   Hasan

Maciej J. Ciesielski

FSM Decomposition and Functional Verification ofFSM Networks

This paper presents a methodology and a tool box for system-level partitioning in the behavioral domain. The methodologyis based on an extended finite state machine model. Partitioning is achieved interactively through the application of fivesystem-level transformation primitives: MOVE, MERGE, SPLIT, CUT and MAP. This scheme allows an interactiveexploration of the solution space. The result of the partitioning is a set of interconnected and heterogeneous sub-systems.The partitioning tool box which has been developed is named PARTIE PARTIF includes an evaluation feedback loop thathelps the designer estimate the quality of the design.

Tarek Ben Ismail

Kevin   O&#39;Brien

Ahmed  Jerraya

PARTIF: Interactive System-level Partitioning

In this article we will be discussing the utilization of decomposition and reduction for development of algorithms. We willassume that a given problem instance can be somehow broken up into two smaller instances that can be solved separately.As a special case of decomposition we will define a reduction, i.e. such a decomposition that one of the resulting instancesis trivial. We will define several versions of decomposition and reduction in a hierarchical way. Different kinds will bedistinguished by their ability to preserve an optimal solution of the original instance. General schema of an algorithmutilizing the proposed notions will be introduced and a case-study demonstrating the adaptation of this schema for thecovering problem will be provided.

Michal  Serv&#237;t

Jan  Zamazal

Decomposition and Reduction: GeneralProblem-Solving Paradigms

During the last decade, many different approaches have been proposed to solve the multiple-level synthesis problem withdifferent minimum functionally complete systems of primitive logic blocks. The most popular of them is the division-basedapproach. However, modem microelectronic technology provides a large variety of building blocks which considerablydiffer from those typically considered. The traditional methods are therefore not suitable for synthesis with many modembuilding blocks. Furthermore, they often fail to find global optima for complex designs and leave unconsidered someimportant design aspects. Some of their weaknesses can be eliminated without leaving the paradigm they are based on, otherones are more fundamental. A paradigm which enables efficient exploitation of the opportunities created by themicroelectronic technology is the general decomposition paradigm. The aim of this paper is to analyze and compare thegeneral decomposition approach and the division-based approach. The most important advantages of the generaldecomposition approach are its generality (any network of any building blocks can be considered) and totality (all importantdesign aspects can be considered) as well as handling the incompletely specified functions in a natural way. In many cases,the general decomposition approach gives much better results than the traditional approaches.

Frank   Volf

Mario  Stevens

Division-Based Versus General Decomposition-Based Multiple-Level Logic Synthesis

Guest Editor&#39;s Introduction

Decomposition of system behavior along functional boundaries into interacting sequential components is a key step in
top-down system design. In this paper, we present sequential decomposition, a method for factoring sequential components
from a system specification based on interface specifications of the components. The resulting components can be
independently synthesized, or realized using off-the-shelf components. We introduce interface specification language (ISL),
based on finite-state machine semantics, to specify the input/output behavior of synchronous sub-systems. A component is
factored from a system by embedding an implementation of the complement of its interface into the system description. The
composition of a machine with its complement is shown to be isomorphic to the machine, and the composition of a machine
with an implementation of its component is shown to be a safe interaction. We apply sequential decomposition to a
non-trivial example, a special-purpose computer with Scheme programming language primitives as its instructions.

Kamlesh Rath

Venkatesh Choppella

Steven D. Johnson

Decomposition of Sequential Behavior Using
Interface Specification and Complementation

An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in thispaper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representationof the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial andparallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completelyor incompletely specified, single- or multiple-output functions and is suitable for different types of FPGAs includingXILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that,in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.

Tadeusz  &#321;uba

Henry   Selvaraj

A General Approach to Boolean FunctionDecomposition and its Application in FPGABasedSynthesis

This paper introduces a new design approach that combines stages of logic and physical design. The logic function issynthesized and mapped to a two-dimensional array of logic cells. This array generalizes PLAs, XPLAs and cellular Maitracascades. Each cell can be programmed to a wire, an inverter, or a two-input AND, OR or EXOR gate (with any subset ofinputs negated). The gate can take any output of four neighbor cells and four neighbor buses as its inputs, and sends its resultback to them. This two-dimensional geometrical model is well suited for both fine-grain FPGA realization and sea-of-gatescustom ASIC layout. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, andproduces a rectangularly shaped structure of (mostly) locally connected cells. Two stages: restricted factorization, andcolumn folding, are discussed in more details to illustrate our general methodology.

Ning  Song

Marek A. Perkowski

Malgorzata  Chrzanowska-Jeske

Andisheh  Sarabi

A New Design Methodology for Two-DimensionalLogic Arrays

This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introducedfamilies include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams canprovide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams(KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and arecreated here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction ofKDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families offunctional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean KroneckerTernary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuitrealization. There are two variants of each of the last two families: canonical and non-canonical. While the canonicaldiagrams can be used as efficient general-purpose Boolean function representations, the non-canonical variants are alsoapplicable to incompletely specified functions and create don&#39;t cares in the process of the creation of the diagram.. They leadto even more compact circuits in logic synthesis and technology mapping.

Andisheh   Sarabi

Ingo  Sch&#228;fer

Multi-Level Logic Synthesis Based on KroneckerDecision Diagrams and Boolean Ternary DecisionDiagrams for Incompletely Specified Functions

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