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High Performance Design Automation of VLSI Interconnects
Guest Editor: Jun-Dong Cho- Guest Editorial, Jun-Dong Cho
Volume 7 (1998), Issue 1, Pages i-iii - Clustering Network Modules with Different Implementations for Delay Minimization, Dimitrios Karayiannis and Spyros Tragoudas
Volume 7 (1998), Issue 1, Pages 1-13 - On Rectilinear Distance-Preserving Trees, Gustavo E. Téllez and Majid Sarrafzadeh
Volume 7 (1998), Issue 1, Pages 15-30 - Automated Synthesis of Skew-Based Clock Distribution Networks, José Luis Neves and Eby G. Friedman
Volume 7 (1998), Issue 1, Pages 31-57 - Power Distribution Synthesis for VLSI, Ashok Vittal and Malgorzata Marek-Sadowska
Volume 7 (1998), Issue 1, Pages 59-72 - Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing, Shashidhar Thakur, Kai-Yuan Chao, and D. F. Wong
Volume 7 (1998), Issue 1, Pages 73-84 - Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing, Kyoung-Son Jhang, Soonhoi Ha, and Chu Shik Jhon
Volume 7 (1998), Issue 1, Pages 85-95 - Placement and Routing for Performance-Oriented FPGA Layout, Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, and Gabriel Robins
Volume 7 (1998), Issue 1, Pages 97-110 - High Performance, Point-to-Point, Transmission
Line Signaling, André Dehon and Thomas F. Knight Jr.
Volume 7 (1998), Issue 1, Pages 111-129