Bozena Kaminska

Marcelo Lubaszewski

Jos&#233; Machado da Silva

Selected Papers from the International Mixed Signals Testing and GHz/Gbps Test Workshop

The research in the area of microelectronic fluidic devices for biomedical applications is rapidly growing. As faults in these devices can have serious personal implications, a system is presented which includes fault tolerance with respect to the synthesized biomaterials (peptides). It can employ presence and purity detection of peptide droplets via current (charge) tests of control electrodes or impedance (phase) measurements using direct sensing electrodes near the peptide collector area. The commercial multielectrode array performs better in pure and impure detection of peptides in impedance and phase. Our two-electrode X-MEF case shows slightly poorer results. In both cases the phase is the best choice for contents detection. If there are presence or purity problems, the location is marked, and repeated peptide synthesis at another collector site is initiated.

H. G. Kerkhoff

X. Zhang

F. Mailly

P. Nouet

H. Liu

A. Richardson

A Dependable Microelectronic Peptide Synthesizer Using Electrode Data

This work presents a new method to estimate the nonlinearity characteristics of analog-to-digital converters (ADCs). The method is based on a nonnecessarily polynomial continuous and differentiable mathematical model of the converter transfer function, and on the spectral processing of the converter output under a sinusoidal input excitation. The simulation and experiments performed on different ADC examples prove the feasibility of the proposed method, even when the ADC nonlinearity pattern has very strong discontinuities. When compared with the traditional code histogram method, it also shows its low cost and efficiency since a significant lower number of output samples can be used still giving very realistic INL signature values.

E. J. Peralías

M. A. Jalón

A. Rueda

Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach

With the growing complexity of wireless systems on chip integrating hundreds-of-millions of transistors, electronic design methods need to be upgraded to reduce time-to-market. In this paper, the test benches defined for design validation or characterization of AMS &#38; RF SoCs are optimized and reused for production testing. Although the original validation test set allows the verification of both design functionalities and performances, this test set is not well adapted to manufacturing test due to its high execution time and high test equipment costs requirement. The optimization of this validation test set is based on the evaluation of each test vector. This evaluation relies on high-level fault modeling and fault simulation. Hence, a fault model based on the variations of the parameters of high abstraction level descriptions and its related qualification metric are presented. The choice of functional or behavioral abstraction levels is discussed by comparing their impact on structural fault coverage. Experiments are performed on the receiver part of a WCDMA transceiver. Results show that for this SoC, using behavioral abstraction level is justified for the generation of manufacturing test benches.

Yves Joannon

Vincent Beroulle

Chantal Robach

Smail Tedjini

Jean-Louis Carbonero

Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test

Built-In RF test is a challenging problem due to the need to measure the values of complex test specifications on-chip with the precision of external RF test equipment. BIT techniques are necessary for guiding system adaptation during field operation. Prior research has demonstrated that embedded RF sensors can generate significant information about RF circuit performance. In this paper, we propose a test methodology that enables efficient BIT and BIT-enabled tuning of RF systems. A test generation approach is developed that co-optimizes the applied test stimulus, the type of embedded sensors, and the system response capture mechanisms for maximal accuracy of the BIT procedure. This BIT technique is also used to perform diagnostic testing of the transmitter. The information gathered from diagnosis is used to tune the transmitter for improved performance. Simulation results demonstrate that BIT-assisted diagnosis and tuning can be performed with good accuracy using the proposed methodology.

Vishwanath Natarajan

Rajarajan Senguttuvan

Shreyas Sen

Abhjit Chatterjee

Built-in Test Enabled Diagnosis and Tuning of RF Transmitter Systems

The test of radiofrequency (RF) integrated circuits at their ever-increasing operating frequency range requires sophisticated test equipment and is time-consuming and, therefore, very expensive. This paper introduces a new method combining low-frequency actuation signal as test stimuli and signal envelope detection applied on the RF output signal in order to provide a low-cost mean for production testing of RF MEMS switches embedded in system-in-package (SiP) devices. The proposed approach uses the principle of alternate test that replaces conventional specification-based testing procedures. The basic idea is to extract the high-frequency characteristics of the switch from the signal envelope of the response. Output parameters like &#x201c;on&#x201d; and &#x201c;off&#x201d; transition time are extracted at low frequency and used in a regression process to predict RF conventional specifications like S-parameters. The paper also provides a set of recursive estimation algorithms suitable for online testing. In this context, &#x201c;on&#x201d; and &#x201c;off&#x201d; transition time estimated from the output low-frequency envelope is used as test metrics and is concurrently updated using recursive algorithms. Validation results obtained on a capacitive RF switch model are presented.

E. Simeu

H. N. Nguyen

P. Cauvet

S. Mir

L. Rufer

R. Khereddine

Using Signal Envelope Detection for Online and  Offline RF MEMS Switch Testing

We describe the use of microelectromechanical system (MEMS) switches and SiGe logic devices for both passive and active loopback testing of wide data buses at rates up to 6.4&#x2009;Gbps per signal. Target applications include HyperTransport, fully buffered DIMM, and PCI Express, among others. Recently introduced MEMS devices provide <svg style="vertical-align:-0.30096pt;width:10.825px;" id="M1" height="8.8500004" version="1.1" viewBox="0 0 10.825 8.8500004" width="10.825"  xmlns="http://www.w3.org/2000/svg">
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</svg>7&#x2009;GHz bandwidth in a very small package (needed to handle wide buses). SiGe logic supports <svg style="vertical-align:-0.30096pt;width:10.825px;" id="M2" height="8.8500004" version="1.1" viewBox="0 0 10.825 8.8500004" width="10.825"  xmlns="http://www.w3.org/2000/svg">
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</svg>7&#x2009;Gbps signals when active shaping of the waveform is required. Each loopback module typically supports between 9 and 16 differential channels. Multiple cards are used to handle applications with very wide buses or multiple ports.  Passive cards utilize MEMS for switching between the loopback (self-test) mode and traditional automated test equipment (ATE) source/receiver channels. Future active card designs may provide additional waveform-shaping functions, such as buffering, amplitude attenuation/modulation, deskew, delay adjustment, jitter injection, and so forth. The modular approach permits precalibration of the loopback electronics and easy reconfiguration between debug or characterization testing and high-volume production screening.

D. C. Keezer

D. Minier

P. Ducharme

D. Viens

G. Flynn

J. McKillop

MEMS Switches and SiGe Logic for Multi-GHz Loopback Testing

Standard production test techniques for ADC require an ATE with an arbitrary waveform generator (AWG) with a resolution at least 2 bits higher than the ADC under test resolution. This requirement is a real issue for the new high-performance ADCs. This paper proposes a test solution that relaxes this constraint. The technique allows the test of ADC harmonic distortions using only low-cost ATE. The method involves two steps. The first step, called the learning phase, consists in extracting the harmonic contributions from the AWG. These characteristics are then used during the second step, called the production test, to discriminate the harmonic distortions induced by the ADC under test from the ones created by the generator. Hardware experimentations are presented to validate the proposed approach.

V. Kerzérho

S. Bernard

F. Azaïs

M. Renovell

M. Comte

O. Chakib

ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator

A test technique for capacitive MEMS accelerometers and electrostatic microactuators, based on the measurement of pull-in voltages and resonance frequency, is described. Using this combination of measurements, one can estimate process-induced variations in the device layout dimensions as well as deviations from nominal value in material properties, which can be used either for testing or device diagnostics purposes. Measurements performed on fabricated devices confirm that the 250&#x2009;nm overetch observed on SEM images can be correctly estimated using the proposed technique.

L. A. Rocha

L. Mol

E. Cretu

R. F. Wolffenbuttel

J. Machado da Silva

A Pull-in Based Test Mechanism for Device Diagnostic and Process Characterization

In previous works of these authors, a technique for doing single-fault diagnosis in linear analog circuits was developed. Under certain conditions, one of them assuming <i>nominal</i> values for the circuit parameters, it was shown that only two measurements taken on two selected circuit nodes, at a single frequency, were needed to detect and diagnose any parametric fault. In this paper, the practical value of the technique is improved by extending the application to the diagnosis of faults in circuits with parameters subject to <i>tolerance</i>. With this in mind, single parametric faults with several strengths are randomly injected in the circuit under study and, afterwards, these faults are diagnosed (or the diagnosis fails). Results are reported on a simple active filter. Conclusions are drawn about the robustness and effectiveness of the technique.

José A. Soares Augusto

Carlos Beltrán Almeida

A Tool for Single-Fault Diagnosis in Linear Analog Circuits with Tolerance Using the T-Vector Approach

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Selected Papers from the International Mixed Signals Testing and GHz/Gbps Test Workshop

Selected Papers from the International Mixed Signals Testing and GHz/Gbps Test Workshop

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