We present the design for the two VLSI components used in a processor-to-memory interconnection network fora shared memory system. These components allow the combining of requests that are destined to the same memorylocation. The design contains both semi-systolic queues and an associative &#8220;wait buffer.&#8221; Transition equations andschematics of the critical pieces of the design are included.

Susan R. Dickey

Richard  Kenner

Design of Components for a Low Cost CombiningSwitch

A central problem in building large scale parallel machines is the design of the interconnection network. Interconnectionnetwork design is largely constrained by packaging technology. We start with a generic set of packagingrestrictions and evaluate different network organizations under a random traffic model. Our results indicate thatcustomizing the network topology to the packaging constraints is useful. Some of the general principles that ariseout of this study are: 1) Making the networks denser at the lower levels of the packaging hierarchy has a significantpositive impact on global communication performance, 2) It is better to organize a fixed amount of communicationbandwidth as a smaller number of high bandwidth channels, 3) Providing the processors with the ability to toleratelatencies (by using multithreading) is very useful in improving performance.

M. T. Raghunath

Abhiram  Ranade

Designing Interconnection Networks forMulti-level Packaging

Pradip K. Srimani

Guest Editor&#39;s Introduction

A new hypercube-like topology, called the hyper Petersen (HP) network, is proposed and analyzed, which isconstructed from the well-known cartesian product of the binary hypercube and the Petersen graph of ten nodes.This topology is an attractive candidate for multiprocessor interconnection having such desirable properties asregularity, high symmetry and connectivity, and logarithmic diameter. For example, an n-dimensional hyper Petersennetwork, <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>, with N&#61;1.25 * <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msup><mml:mn>2</mml:mn><mml:mi>n</mml:mi></mml:msup></mml:mrow></mml:math> nodes is a regular graph of degree and node-connectivity n and diameter n&#8211;1, whereas an (n&#8211;1)-dimensional binary hypercube, <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>Q</mml:mi><mml:mrow><mml:mi>n</mml:mi><mml:mo>&#x2212;</mml:mo><mml:mn>1</mml:mn></mml:mrow></mml:msub></mml:mrow></mml:math>, with the same diameter covers only <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msup><mml:mn>2</mml:mn><mml:mrow><mml:mi>n</mml:mi><mml:mo>&#x2212;</mml:mo><mml:mn>1</mml:mn></mml:mrow></mml:msup></mml:mrow></mml:math> nodes, eachof degree (n&#8211;1). Thus the HP topology accommodates 2.5 times extra nodes than <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>Q</mml:mi><mml:mrow><mml:mi>n</mml:mi><mml:mo>&#x2212;</mml:mo><mml:mn>1</mml:mn></mml:mrow></mml:msub></mml:mrow></mml:math> at the cost of increasingthe node-degree by one. With the same degree and connectivity of n, the diameter of the <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math> network is one lessthan that of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>Q</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>, yet having 1.25 times larger number of nodes.Efficient routing and broadcasting schemes are presented, and node-disjoint paths in <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>, are computed evenunder faulty conditions. The versatility of the hyper Petersen networks is emphasized by embedding rings, meshes,hypercubes and several tree-related topologies into it. Contrary to the hypercubes, rings of odd lengths, and acomplete binary tree of height n&#8211;1 permit subgraph embeddings in <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>.

Sajal K. Das

Sabine  &#214;hring

Amit K. Banerjee

Embeddings into Hyper Petersen Networks: YetAnother Hypercube-Like Interconnection Topology

It is well known that the hypercube has a rich set of good properties, and consequently it has been recognized an
ideal structure for parallel computation. Nevertheless, according to the current VLSI technology, the implementation
feasibility of the hypercube remains questionable when the size of the hypercube becomes large. Recent research
efforts have been concentrated on finding good alternatives to the hypercube. The star graph was shown having
many desirable properties of the hypercube, and in several aspects, the star graph is better than the hypercube.
However, we observe that the star graph as a network has several disadvantages, compared with the hypercube. In
this paper, we propose a class of new networks, the star-hypercube hybrid networks (or the SH networks). The SH
network is a simple combination of both the star graph and the hypercube. This class of networks contains the
star graph and the hypercube as subclasses. We show that the SH network is an efficient and versatile network for
parallel computation, since it shares properties of both the hypercube and the star graph, and remedies several
major disadvantages of the hypercube and the star graph. This class of networks provide more flexibility in choosing
the size, degree, number of vertices, degree of fault tolerance, etc. in designing massively parallel computing
structures feasible for VLSI implementations.

S. Q. Zheng

B. Cong

S. Bettayeb

Trade-Off Considerations in Designing Efficient VLSI
Feasible Interconnection Networks

Least Common Ancestor Networks (LCANs) are introduced and shown to be a class of networks that include fattrees,baseline networks, SW-banyans and the router networks of the TRAC 1.1 and 2.0 and the CM-5. SomeLCAN properties are stated and the circuit-switched permutation routing capabilities of an important subclass areanalyzed. Simulation results for three permutation classes verify the accuracy of an iterative analysis for a randomizedrouting strategy. These results indicate that the routing strategy provides highly predictable router performancefor all permutations. An off-line routing algorithm is also given, and it is shown how to realize certain classes ofpermutations by adapting Nassimi and Sahni&#39;s, and Raghavendra and Boppana&#39;s self-routing algorithms for Benesnetworks.

Isaac D. Scherson

Chi-Kai  Chien

Least Common Ancestor Networks

We derive some properties of the star graph in this paper. In particular, we compute the number of nodes at distance ifrom a fixed node e in a star graph. To this end, a recursive formula is first obtained. This recursive formula is,in general, hard to solve for a closed form solution. We then study the relations among the number of nodes atdistance i to node e in star graphs of different dimensions. This study reveals a very interesting relation amongthese numbers, which leads to a simple homogeneous linear recursive formula whose characteristic equation iseasy to solve. Thus, we get a systematic way to obtain a closed form solution with given initial conditions for anyfixed i.

Ke  Qiu

Selim G. Akl

On Some Properties of the Star Graph

High-performance parallel systems demand a high-performance interconnect so that their component parts canexchange data and synchronise efficiently. The interconnect must be cheap, and must also scale well in bothperformance and cost relative to the system size. In this paper we describe the rationale, architecture and operationof the STC104, the first commercially available, general-purpose interconnect chip. The serial protocols used bythe device are described, followed by an overview of the microarchitecture, The operation of the fundamental blockis outlined, including the response to error conditions. Chip-wide design issues and design methodology are discussed,and finally various aspects of performance are calculated.

Peter W. Thompson

Julian D. Lewis

The STC104 Packet Routing Chip

We examine the cost in router complexity of adaptivity and virtual lanes in wormhole routers, using f-flat adaptive
routers (based on a generalization of planar-adaptive routing) which include routers with a range of routing
freedom. Our studies show that adaptivity is expensive because it requires additional virtual channels and much
larger crossbar switches for both adaptivity and deadlock prevention. Increases of 50 to 100% in channel utilization
are required to justify additional degrees of routing freedom.Three internal router architectures for virtual lanes are examined and the fully expanded crossbar is found to be
most effective because it gives simplest control and minimal internal blocking. Examining router designs with from
1–16 virtual lanes indicates that 30% improvements in channel utilization are required to justify each additional
virtual lane. These studies combined with published simulation results indicate that only modest numbers of virtual
lanes are likely to be cost effective.

Kazuhiro Aoyama

Andrew A. Chien

The Cost of Adaptivity and Virtual Lanes in a
Wormhole Router

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