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Field Programmable Gate Arrays
Guest Editor: Dinesh Bhatia- Field-Programmable Gate Arrays, Dinesh Bhatia
Volume 4 (1996), Issue 4, Pages i-ii - Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays, Stephen Brown, Muhammad Khellah, and Guy Lemieux
Volume 4 (1996), Issue 4, Pages 275-291 - A Sea-of-Gates Style FPGA Placement Algorithm, Kalapi Roy, Bingzhong (David) Guan, and Carl Sechen
Volume 4 (1996), Issue 4, Pages 293-307 - A Timing-Driven Partitioning System for Multiple FPGAs, Kalapi Roy and Carl Sechen
Volume 4 (1996), Issue 4, Pages 309-328 - DP-FPGA: An FPGA Architecture Optimized for Datapaths, Don Cherepacha and David Lewis
Volume 4 (1996), Issue 4, Pages 329-343 - Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation, Srilata Raman, C. L. Liu, and Larry G. Jones
Volume 4 (1996), Issue 4, Pages 345-355