This paper presents new heuristic search algorithms for searching combined rectilinear(L1) and link metric shortest paths in the presence of orthogonal obstacles. The Guided Minimum Detour (GMD)algorithm for L1 metric combines the best features of mazerunningalgorithms and line-search algorithms. The Line-by-Line Guided MinimumDetour (LGMD) algorithm for L1 metric is a modification of the GMD algorithm thatimproves on efficiency using line-by-line extensions. Our GMD and LGMD algorithmsalways find a rectilinear shortest path using the guided A* search method withoutconstructing a connection graph that contains shortest paths. The GMD and the LGMDalgorithms can be implemented in O(m+eloge+NlogN)and O(eloge+NlogN) time,respectively, and O(e+N) space, where m is the total number of searched nodes, e is thenumber of boundary sides of obstacles, and N is the total number of searched linesegments. Based on the LGMD algorithm, we consider not only the problems of findinga link metric shortest path in terms of the number of bends, but also the combined L1metric and link metric shortest path in terms of the length and the number of bends.

Joon Shik Lim

S. Sitharama Iyengar

Si-Qing  Zheng

Finding Combined L1 and Link Metric ShortestPaths in the Presence of Orthogonal Obstacles:A Heuristic Approach

Stephan  Olariu

Rong  Lin

Guest Editorial

The reconfigurable mesh (RN-MESH) can solve a large class of problems in constanttime, including problems that require logarithmic time by other, even shared memory,models such as the PRAM with a similar number of processors [3]. In this work we showthat for the RN-MESH these constants can always be reduced to one, still using apolynomial number of processors. Given a reconfigurable mesh that computes a set ofvalues in constant time, we show that it can be simulated by a single step reconfigurablemesh with maximum size that is polynomial in the size of the original mesh. The proof isconstructive, where the construction of the single step RN-MESH holds for therelatively weak undirected RN-MESH model. In this model broadcasts made on busesarrive at all nodes that belong to the undirected connected component of thetransmitting processor. A result similar to the one that is obtained in this work waspreviously obtained for the directed reconfigurable mesh model (DRN) [5]. However,the construction for the DRN-MESH relies on the fact that the buses are directed, andthus cannot be applied to the undirected case. In addition, the construction presentedhere is simpler and uses significantly fewer processors than the one obtained for theDRN-MESH.

Yosi  Ben-Asher

Assaf  Schuster

Single Step Undirected Reconfigurable Networks

String matching (SM) problem is to find the occurrences of a pattern within a text. Avanable length don&#39;t care (VLDC) is a special symbol, not belonging to a finite alphabet&#8721; but in &#8721;*. Each VLDC in the pattern can match any substring in the text. Given arun-length coded text of length 2n over &#8721; and a run-length coded pattern of length 2mover &#8721;*, this paper first presents an O(1) time parallel SM algorithm for run-lengthcoded strings with VLDCs on a reconfigurable mesh (RM) using O(nm) processors.Consider the hardware limitation in VLSI implementation. In order to be suitable forVLSI modular implementation, a partitionable parallel algorithm on the RM withlimited processors is further presented. For N &#60; n and M &#60; m, the SM for run-lengthcoded strings with VLDCs can be solved in O<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:mover accent="true"><mml:mi>X</mml:mi><mml:mo>&#x005E;</mml:mo></mml:mover><mml:mover accent="true"><mml:mi>Y</mml:mi><mml:mo>&#x005E;</mml:mo></mml:mover></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math>time on the RM usingO(NM)(&#61; O((nm)/(<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:mover accent="true"><mml:mi>X</mml:mi><mml:mo>&#x005E;</mml:mo></mml:mover><mml:mover accent="true"><mml:mi>Y</mml:mi><mml:mo>&#x005E;</mml:mo></mml:mover></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math>)) processors, where <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mover accent="true"><mml:mi>X</mml:mi><mml:mo>&#x005E;</mml:mo></mml:mover></mml:math> &#61; [(n &#8211; 1)/(N &#8211; 1)] and <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mover accent="true"><mml:mi>Y</mml:mi><mml:mo>&#x005E;</mml:mo></mml:mover></mml:math>&#61; [(m &#8211; 1)/(M &#8211; 1)].

Hsiu-Niang  Chen

Kuo-Liang  Chung

Partitionable Bus-based String-matching Algorithmfor Run-length Coded Strings With VLDCs

Algorithms for multiplying several types of sparse n x n-matrices on dynamically
reconfigurable n x n-arrays are presented. For some classes of sparse matrices constant
time algorithms are given, e.g., when the first matrix has at most kn elements in each
column or in each row and the second matrix has at most kn nonzero elements in each
row, where k is a constant. Moreover, O(k<mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msqrt><mml:mi>n</mml:mi></mml:msqrt></mml:mrow></mml:math>
) algorithms are obtained for the case that
one matrix is a general sparse matrix with at most kn nonzero elements and the other
matrix has at most k nonzero elements in every row or in every column. Also a lower
bound of Ω(<mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msqrt><mml:mrow><mml:mi>K</mml:mi><mml:mi>n</mml:mi></mml:mrow></mml:msqrt></mml:mrow></mml:math>
) is proved for this and other cases which shows that the algorithms are
close to the optimum.

Martin Middendorf

Hartmut Schmeck

Heiko Schröder

Gavin Turner

Multiplication of Matrices With Different Sparseness Properties on Dynamically Reconfigurable Meshes

Extensive comparative analysis is carried out of various mesh-connected architectures
that contain sparse broadcast buses for low-cost, high-performance parallel computing.
The two basic architectures differ in the implementation of bus intersections. The first
architecture simply allows row/column bus crossovers, whereas the second architecture
implements such intersections with switches that introduce further flexibility. Both
architectures have lower cost than the mesh with multiple broadcast, which has buses
spanning each row and each column, but the former architectures maintain to high
extent the powerful properties of the latter mesh. The architecture that employs switches
for the creation of separable buses is even shown to often perform better than the
higher-cost mesh with multiple broadcast. Architectures with separable buses that
employ store-and-forward routing often perform better than architectures with
contiguous buses that employ the high-cost wormhole routing technique. These
architectures are evaluated in reference to cost, and efficiency in implementing several
important operations and application algorithms. The results prove that these
architectures are very promising alternatives to the mesh with multiple broadcast while
their implementation is cost-effective and feasible.

Sotirios G. Ziavras

Investigation of Various Mesh Architectures
With Broadcast Buses for High-Performance Computing

Most algorithms for reconfigurable meshes (R-meshes) are based on the divide-and-conquer(DAC) strategy. Although the strategy per se does not require the subproblemsto be equal in size, existing DAC algorithms for R-meshes do divide the problemapproximately evenly. This paper demonstrates that dividing a problem evenly is notnecessarily a good way to decompose a problem. There are occasions on which anirregular decomposition scheme may be preferable. We take this approach and obtain anew sorting algorithm. Our sorting algorithm has several strengths: it is simple, scalable,and as broadcast-efficient as the best known result.

Ten H. Lai

Ming-Jye  Sheng

Sorting on Reconfigurable Meshes:An Irregular Decomposition Approach

We present novel asynchronous VLSI comparator schemes which are based on recently
proposed, reconfigurable shift switch logic and the traditional (precharged) CMOS
domino logic. The schemes always produce a semaphore as a by-product of the process
to indicate the end of domino process, which requires no additional delay and a minimal
number of additional devices. For a large percentage of inputs the computations are
much faster than traditional synchronous comparators due to the full utilization of the
inherent speed of the circuits. Also the schemes are simple, area compact and stable.

R. Lin

S. Olariu

Reconfigurable Shift Switching Parallel Comparators

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High Performance Bus-Based Architectures

High Performance Bus-Based Architectures

Articles

Finding Combined L₁ and Link Metric Shortest Paths in the Presence of Orthogonal Obstacles: A Heuristic Approach

Guest Editorial

Single Step Undirected Reconfigurable Networks

Partitionable Bus-based String-matching Algorithm for Run-length Coded Strings With VLDCs

Multiplication of Matrices With Different Sparseness Properties on Dynamically Reconfigurable Meshes

Investigation of Various Mesh Architectures With Broadcast Buses for High-Performance Computing

Sorting on Reconfigurable Meshes: An Irregular Decomposition Approach

Reconfigurable Shift Switching Parallel Comparators