We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS)
techniques for power optimizations. We introduce a fast heuristic for choosing gates for
sizing and voltage scaling such that the total power is minimized under delay constraints.
We also use a more accurate estimate for determining the power dissipation of
the circuit by taking into account the short circuit power along with the dynamic power.
A better model of the short circuit power is used which takes into account the load
capacitance of the gates. Our results show that the combination of VS and GS perform
better than the techniques applied in isolation. An average power reduction of 73% is
obtained when decisions are taken assuming dynamic power only. In contrast, average
power reduction is 77% when decisons include the short circuit power dissipation.

Anshuman Nayak

Malay Haldar

Prith Banerjee

Chunhong Chen

Majid Sarrafzadeh

Power Optimization of Delay Constrained Circuits

Jun-Dong  Cho

Preface

We present a new approach to the power modeling of functional modules, referred to as
the backward propagated capacitance model, for estimating the power consumption of
VLSI systems that are described at the register transfer level (RTL). To construct the
proposed model, we investigate the effect of the module's internal capacitance on power
consumption at the gate level. Then, we store the effect in a library in terms of the
equivalent input capacitance of the module. The equivalent input capacitance is used to
compute the module's power without the lower level elaboration during the power
analysis of the RTL system. In the experiment using benchmark functional modules, the
proposed model showed the absolute modeling error of 1.39% on average. For the
benchmark RTL systems, the proposed model exhibited the absolute error of 3.04% in
power estimation on average. If signal characteristics deviate from the modeling
condition, the modeling error may increase. Experimental results show that the
modeling accuracy can be improved greatly by using a simple compensation method.

Jung Yun Choi

Young Hwan Kim

Kyoung-Rok Cho

Backward Propagated Capacitance Model for Register Transfer Level Power Estimation

We present an effective switching activity modeling and estimation technique forcomponents under resource sharing. The model uses word-level signal statistics togenerate a single parameter, called signal strength. By using the signal strength, we canconstruct power models for the both cases of sharing and non-sharing of computingresources. The model enables us to effectively estimate switching activity at higher levelof design abstraction. We have conducted several experiments using both synthetic andreal data to evaluate our method. We have compared competing architectures for theirrelative power consumption for different components. The results show that averagedifference between the proposed method and very accurate power simulation (asopposed to switching estimation) using PowerMill is up to 12&#37;.

Lih-Yih  Chiou

Khurram  Muhammand

Kaushik  Roy

Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications

We present a novel method for estimating the power of sequential CMOS circuits.Symbolic probabilistic power estimation with an enumerated state space is used toestimate the average power switched by the circuit. This approach is more accurate thansimulation based methods. Automatic circuit partitioning and state space explorationprovide improvements in run-time and storage requirements over existing approaches.Circuits are automatically partitioned to improve the execution time and to allow largercircuits to be processed. Spatial correlation is dealt with by minimizing the cutsetbetween partitions which tends to keep areas of reconvergent fanout in the samepartition. Circuit partitions can be recombined using our combinational estimationmethods which allow the exploitation of knowledge of probabilities of the circuit inputs.We enumerate the state transition graph (STG) incrementally using state spaceexploration methods developed for formal verification. Portions of the STG aregenerated on an as-needed basis, and thrown away after they are processed. BDDs areused to compactly represent similar states. This saves significant space in the storage ofthe STG. Our results show that modeling the state space is imperative for accuratepower estimation of sequential circuits, partitioning saves time, and incremental statespace exploration saves storage space. This allows us to process larger circuits thanwould otherwise be possible

Miriam  Leeser

Valerie  Ohm

Accurate Power Estimation for Sequential CMOS Circuits Using Graph-based Methods

This paper presents a state assignment algorithm with the objective of lower energyalong with area comparable to the area-targeting state assignments such as JEDI. Theunderlying framework is MUSTANG&#39;s complete weighted graph with weights representingstate affinity. The weight computation phase estimates the computation energyof potential common cubes using steady state probabilities for transitions. The weightcomputation phase also identifies a large set of potential state cliques, which are incorporatedinto a recursive bipartitioning based state assignment procedure. Reuse ofcliques identified by the weight computation phase results in a faster and efficient stateassignment. The energy targeting weights result in &#8776;9&#37; lower area and 18&#37; lowerpower than area targeting weights in JEDI over 29 MCNC Logic Synthesis &#145;93 benchmarks.The clique based state assignment performs almost as well as the annealingbased state assignment in JEDI, and takes only about half as much time.

Akhilesh  Tyagi

Integrated Area-power Optimal State Assignment

Power consumption in a synchronous FSM (Finite-State Machine) can be reduced by
partitioning it into a number of coupled sub-FSMs where only the part that is involved
in a state transition is clocked. Automatic synthesis of a partitioned FSM includes a
partitioning algorithm and sub-FSM synthesis to an implementation architecture. In
this paper, we first introduce an implementation architecture for partitioned FSMs that
uses gated-clock technique for disabling idle parts of the circuits and asynchronous
controllers for communication between the sub-FSMs. We then describe a new transformation
procedure for the sub-FSM. The FSM synthesis flow has been automated in a
prototype tool that accepts an FSM specification. The tool generates synthesizable RT-level
VHDL code with identical cycle-to-cycle input/output behavior in accordance
with the specification. An average power reduction of 45% has been obtained for a set
standard FSM benchmarks.

Bengt Oelmann

Kalle Tammemäe

Margus Kruus

Mattias O'Nils

Automatic FSM Synthesis for Low-power Mixed Synchronous/Asynchronous Implementation

Power constraints are becoming a critical design issue in the field of portable
microprocessor systems. The impact of software on overall system power is becoming
increasingly important as more and more digital applications are implemented as
embedded systems, part of which are hardware (ASICs) and part software in which a
specific application is executed on a processor. In this paper, a data-dependent
instruction-level power analysis model is presented. It is compared with the average cost
model proposed by Tiwari et al. [1] in both estimation accuracy and characterisation
time. The data-dependent model can be generalised to be applied to generic RISC
processor. Application of the data-dependent model we propose sensibly reduces errors
in estimating software power consumption per clock cycle which is lower than 10%, in
the case of the ST20-C2P core.

Giuseppe Ascia

Vincenzo Catania

Maurizio Palesi

Davide Sarta

An Instruction-Level Power Analysis Model with Data Dependency

The advantages of a Multi-Chip Module (MCM) product are its low-power and small-size.
But the design of an MCM system usually requires weeks of engineering effort, thus
we need a generic MCM substrate with programmable interconnections to accelerate
system prototyping. In this paper, we propose a Symmetric and Programmable MCM
(SPMCM) substrate for this purpose. This SPMCM substrate consists of a symmetrical
array of slots for bare-chip attachment and Field Programmable Interconnect Chips
(FPICs) for substrate routing. Experimental results demonstrate that our FPIC polygonal
routing module uses 12% less switches than the conventional routing module
for interconnecting bare-chip slots with 84 pads. Also, experiments are conducted to
determinate proper parameters for the VLSI implementation of our FPIC.

Mao-Hsu Yen

Sao-Jie Chen

Sanko H. Lan

Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System

Multimedia algorithms deal with enormous amounts of data transfers and storage,resulting in huge bandwidth requirements at the off-chip memory and system bus level.As a result the related energy consumption becomes critical. Even for execution time thebottleneck can shift from the CPU to the external bus load. This paper demonstratesa systematic software approach to reduce this system bus load. It consists of source-to-sourcecode transformations, that have to be applied before the conventional ILPcompilation. To illustrate this we use a cavity detection algorithm for medical imaging,that is mapped on an Intel Pentium&#174; II processor.

Koen  Danckaert

Chidamber  Kulkarni

Francky  Catthoor

Hugo  De Man

Vivek  Tiwari

A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms

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