As VLSI technology enters the nanometer regime, the design complexity is rapidly increasing with timing, power, routability, and reliability. Salient design automation techniques for scalable SoC design and verification solutions that could greatly improve the design quality are highly desired.

This special issue is dedicated to the research problems in all aspects of System-on-Chip (SoC) implementation and verification. New optimization, simulation, and verification techniques containing theoretical and/or applied contributions that emphasize the scalability to future large designs are all welcome. This special issue will become an international forum for researchers to summarize the state-of-the-art development in scalable VLSI design and verification algorithms and methodologies. Topics of interest include, but are not limited to:

• Physical synthesis (interconnect optimization, buffer insertion, gate sizing, vt assignment, layer assignment, etc.)
• Floorplanning and placement
• Routing (congestion analysis, global and detail routing techniques)
• Clock synthesis
• Design for manufacturability and variability
• Functional and formal verification
• System level modeling and simulation
• Electronic System Level (ESL) design methodologies, tools, languages, and flow
• Low Power-aware systems design and verification
• 3D VLSI/NoC design and verification flow/synthesis
• ASIC emulation and FPGA prototyping
• IP specification, creation, and reuse
• New ATPG and DFT solutions

Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/vlsi/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable: