Volume 2 [31 articles]

Digital Hardware Testing [8 articles]

• Partitioning Techniques for Built-In Self-Test Design, Chien-In Henry Chen
  Volume 2 (1994), Issue 3, Pages 185-198
• An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits, Hyung K. Lee and Dong S. Ha
  Volume 2 (1994), Issue 3, Pages 199-207
• Techniques for Self-Checking Combinational Logic Synthesis, Fadi Busaba and Parag K. Lala
  Volume 2 (1994), Issue 3, Pages 209-221
• A Quadratic Programming Approach to Estimating the Testability and Random or Deterministic Coverage of a VLSl Circuit, H. Farhat and S. From
  Volume 2 (1994), Issue 3, Pages 223-231
• TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing, C. P. Ravikumar and H. Rasheed
  Volume 2 (1994), Issue 3, Pages 233-239
• SEGMA: A Simulated Evolution Gate-Matrix Layout Algorithm, Chi-Yu Mao and Yu Hen Hu
  Volume 2 (1994), Issue 3, Pages 241-257
• An Improved Data Flow Architecture for Logic Simulation Acceleration, A. Mahmood, J. Herath, and J. Jayasumana
  Volume 2 (1994), Issue 3, Pages 259-265
• Modular Scheme for Designing Special Purpose Associative Memories and Beyond, A. R. Hurson and S. Pakzad
  Volume 2 (1994), Issue 3, Pages 267-286