IET Computers & Digital Techniques

The asynchronous advantage actor-critic (A3C) algorithm is widely regarded as one of the most effective and powerful algorithms among various deep reinforcement learning algorithms. However, the distributed and asynchronous nature of the A3C algorithm brings increased algorithm complexity and computational requirements, which not only leads to an increased training cost but also amplifies the difficulty of deploying the algorithm on resource-limited field programmable gate array (FPGA) platforms. In addition, the resource wastage problem caused by the distributed training characteristics of A3C algorithms and the resource allocation problem affected by the imbalance between the computational amount of inference and training need to be carefully considered when designing accelerators. In this paper, we introduce a deployment strategy designed for distributed algorithms aimed at enhancing the resource utilization of hardware devices. Subsequently, a FPGA architecture is constructed specifically for accelerating the inference and training processes of the A3C algorithm. The experimental results show that our proposed deployment strategy reduces resource consumption by 62.5% and decreases the number of agents waiting for training by 32.2%, and the proposed A3C accelerator achieves 1.83× and 2.39× improvements in speedup compared to CPU (Intel i9-13900K) and GPU (NVIDIA RTX 4090) with less power consumption respectively. Furthermore, our design shows superior resource efficiency compared to existing works.

This article proposes an efficient and accurate embedded motor imagery-based brain–computer interface (MI-BCI) that meets the requirements for wearable and real-time applications. To achieve a suitable accuracy considering hardware constraints, we explore BCI transducer algorithms, among which Infinite impulse response (IIR) filter, common spatial pattern, and support vector machine are used to preprocess, extract features, and classify data, respectively. With our hardware implementation of these tasks, we have achieved an accuracy of 77%. Our system is designed at register transfer level (RTL) targeting an ASIC implementation, which significantly decreases power consumption, latency, and area compared to the state-of-the-art (SoA) architectures for embedded BCI systems. To this end, we fold IIR filters using time-shared and RAM-based techniques and use hardware-friendly algorithms for the implementation of other tasks. The RTL design is realized on 45 nm CMOS technology consuming 4 mW power and 0.25 mm² area, which outperforms the SoA platforms for embedded BCI systems. To further illustrate the outperformance of our design, the proposed architecture is implemented on Virtex-7 field program gate array as a prototyping platform consuming 6 μJ energy with 1.52% area utilization.

One of the problems in the blockchain is the formation of increasingly large data (big data) because each block must store all the transactions it makes. With the problem of the appearance of extensive data (big data), many studies aim to maintain the data in small amounts. This research combines a sorting data technique and a proper compression technique to obtain efficient data storage on the blockchain. The result of this research is a blockchain platform called Adaptive Shrink and Shard Blockchain (AS²BC), which conceptually and computationally can minimize the use of storage space in the blockchain up to 22 times smaller.