Yasuhisa Omura

Kansai University, Japan


Yasuhisa Omura received the M.S. degree in applied science in 1975 and the Ph.D. degree in electronics in 1984, both from Kyushu University, Japan. He joined the Musashino Electrical Communications Laboratories, NTT, Japan, in 1975. He worked on short‐channel CMOS/SIMOX design, LSI processing, and SOI device modeling. In NTT, he contributed to trial demonstrations of 1 kb and 4 kb CMOS/SIMOX SRAM on the device design and fabrication processing. He moved his position from NTT Atsugi R&D Center to Kansai University, Osaka Prefecture, as a Professor after April 1997, and he is presently working on device physics of ultimately miniaturized MOSFET/SOI, modeling for MOS device design, physics of transport noise, and development of silicon‐based photonic devices. He has published 140 regular papers and 160 international conference proceedings. He is one of authors having published “Device and Circuit Cryogenic Operation for Low Temperature Electronics” (2001, Kluwer Academic Publishers) and “Fully Depleted SOI CMOS Circuits and Technology for Ultralow‐Power Applications,” edited by Y. Sakurai et al. (2006, Springer). He recently published a book entitled SOI Lubistor from IEEE Wiley, 2013. He served the Technical Committee of IEEE International SOI Conference from 1997 to 1998 and now serves the Program Committee of International Symposium on VLSI Technology from 1997 to 2006. In addition, he serves the International Advisory Committee of International Workshop on Low‐Temperature Electronics from 1998. He also serves the voluntary work as the Chair of IEEE EDS Kansai Chapter from 2009 to 2010, the IEEE japan Council, Chapter Operations Comm., Vice Chair and Chair, from 2011 to 2014. Dr. Omura is a Member of the Japan Society of Applied Physics (JSAP), the Physical Society of Japan, and the Electrochemical Society, Fellow of IEEE, and Member of the Institute of Electronics, Information, and Communication Engineers (IEICE).

Biography Updated on 28 February 2015

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