Research Article
Leakage Power Analysis of Domino XOR Gate
Table 2
Leakage power consumption (μW) of four XOR circuits in different Input States and Clock States at 25°C.
| | Inputs | DXN | DXP | DXHL | DXHD | | CLK = 0 | CLK = 1 | CLK = 0 | CLK = 1 | CLK = 0 | CLK = 1 | CLK = 0 | CLK = 1 |
| | , | 2.06 | 3.50 | 1.93 | 1.91 | 1.14 | 1.88 | 0.67 | 0.88 | | , | 2.01 | 3.08 | 1.92 | 2.57 | 1.42 | 4.26 | 0.95 | 1.37 | | , | 2.46 | 3.08 | 1.84 | 2.05 | 1.42 | 4.26 | 0.95 | 1.37 | | , | 2.43 | 3.13 | 2.57 | 2.55 | 1.01 | 2.37 | 0.53 | 1.92 |
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