Research Article
Architecture Analysis of an FPGA-Based Hopfield Neural Network
Algorithm 1
Pseudocode of control unit.
State 0: wait for capture-button | (i) user input | State 1: ENENT = 1; SELINT-EXT = 0; | (i) input data admission | State 2: = 1; SELINT-EXT = 0; | (i) set initial state | State 3: = 1; = 1; | (i) register state at the begin of an epoch | (ii) = 1 while not end | State 4: = 1; SELINT-EXT = count_neuron; | State 5: ENADDER = 1; | State 6: = 1; if count_neuron = neuron_size | then next state = State 7; | else next state = State 4; ++ count_neuron; ++ ; | State 7: ENEND-EPOCH = 1; | (i) register state at the end of an epoch | if converge = 1 then next state = State 0; | else next state = State 3; | end; |
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