Research Article
High Performance Discrete Cosine Transform Operator Using Multimedia Oriented Subword Parallelism
Table 3
Synthesis results of SWP 2D-DCT.
|
90 nm CMOS ASIC |
130 nm CMOS ASIC |
FPGA VirtexII | Nand gates | CP (ns) | Power (mW) | Nand gates | CP (ns) | Power (mW) | CLB | CP (ns) |
| Pretranspose SWP 8-point DCT | 195650 | 9.8 | 7.6 | 160689 | 21.8 | 5.7 | 10790 | 19.8 |
| Posttranspose SWP 8-point DCT | 293476 | 11.1 | 11.4 | 241034 | 25.7 | 8.5 | 16185 | 24.9 |
| Other units | 54347 | 5.7 | 2.1 | 60028 | 10.4 | 2.2 | 4760 | 12.3 |
| Complete SWP DCT operator | 543474 | 11.1 | 21.2 | 461752 | 25.7 | 16.4 | 31735 | 24.9 |
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