Transformation of Holes Emission Paths under Negative Bias Temperature Stress in Deeply Scaled pMOSFETs

Figure 6

The transformation of transience signal from -Step to -RTN could be seen by decreasing the gate bias from −1.7 V to −1.5 V. And the emission time of this trap is obviously decreased from larger than 300 s to about 10 s when gate bias is decreased from −1.7 V to −1.2 V.