Research Article | Open Access

Yu-Chen Li, He-Ming Zhang, Shu-lin Liu, Hui-Yong Hu, "Strain and Dimension Effects on the Threshold Voltage of Nanoscale Fully Depleted Strained-SOI TFETs", *Advances in Condensed Matter Physics*, vol. 2015, Article ID 850383, 6 pages, 2015. https://doi.org/10.1155/2015/850383

# Strain and Dimension Effects on the Threshold Voltage of Nanoscale Fully Depleted Strained-SOI TFETs

**Academic Editor:**Rosa Lukaszew

#### Abstract

A novel nanoscale fully depleted strained-SOI TFET (FD-SSOI TFET) is proposed and exhaustively simulated through Atlas Device Simulator. It is found that FD-SSOI TFET has the potential of improved on-current and steep subthreshold swing. Furthermore, the effect of strain and dimension on the threshold voltage of FD-SSOI TFET is thoroughly studied by developing a model based on its physical definition. The validity of the model is tested for FD-SSOI TFET by comparison to 2D device simulations. It is shown that the proposed model can predict the trends of threshold voltage very well. This proposed model provides valuable reference to the FD-SSOI TFETs design, simulation, and fabrication.

#### 1. Introduction

Recently, minimizing energy consumption in mobile devices, processors, and biomedical electronics is one of the most challenging tasks. TFETs with steep subthreshold swing (less than 60 mV/dec) are considered as a promising device for low power applications [1–5]. However, in traditional TFETs, low on-current in comparison to conventional MOSFETs is the major shortcoming due to the poor tunneling probability of silicon. In addition, average subthreshold swing of traditional TFETs which is important for switch performance needs to be further improved [6]. By using narrow band gap materials, TFETs can achieve improved performance. Tensile strained silicon which has a smaller band gap than silicon and is compatible with conventional silicon processing can help to improve the tunneling currents. SOI technology has some straightforward advantages, such as the absence of latchup in CMOS structures and the reduction of parasitic capacitances. Single-layer strained-SOI (SSOI) structure [7, 8] combines the advantages of strained Si with thin film SOI and is less susceptible to misfit dislocation induced leakage current.

In this work, we propose a novel fully depleted SSOI TFET (FD-SSOI TFET) structure. High on-current can be achieved by introducing SSOI structure, and the average subthreshold swing can be effectively decreased. Moreover, the effect of strain (in terms of equivalent Ge mole fraction in the relaxed SiGe buffer), strained Si layer thickness, gate length, and other device parameters on the threshold voltage of FD-SSOI TFET is thoroughly studied by developing a model based on its physical definition. The results from the model are compared with the simulation results and are found to be in excellent agreement.

#### 2. Device Structure and Simulations

The structure of an FD-SSOI N-TFET is shown in Figure 1, where , , , and represent the source, gate, drain, and substrate electrode, respectively. The device consists of a high- dielectric layer with a thickness of , a strained Si layer with a thickness of , a buried oxide layer with a thickness of , and a gate with a length of .

Simulations are done in Silvaco Atlas, using nonlocal band-to-band tunnelling model for including effect of tunneling, which is the most important model for TFETs simulations. Two other important models that are applied during simulations are the band gap narrowing model and the quantum model (see [9, 10] for more details). The accuracy of these models has already been proven in [10, 11]. In simulations, junctions are ideally abrupt, with the doping concentration of = 10^{20} cm^{−3} in the P^{+}-type source, = 10^{17} cm^{−3} in P^{−}/N^{−}-type body, and = 5 × 10^{18} cm^{−3} in the N-type drain, the gate length is = 50 nm, the gate dielectric thickness is = 3 nm, the strained Si layer thickness is = 10 nm, the gate work function is = 4.5 ev, and the gate leakage is neglected.

In Figure 2, the Atlas simulated band diagrams are shown for a reference silicon TFET () and for a FD-SSOI TFET () in the on-condition. A narrowing of the barrier is seen in the case of the 0.6-equivalent Ge mole fraction device, which increases tunneling probability and hence . Figure 3 shows the transfer characteristics for FD-SSOI TFETs with different strain (equivalent Ge mole fraction in the relaxed SiGe buffer layer). The FD-SSOI TFET devices show large enhancements in the on-state current as compared to silicon TFET. The off-state leakage current is increased with increased strain but still in the fA range. In addition, a remarkable improvement is found in the point and average subthreshold swing, presented in more detail in Figure 4. Point subthreshold swing ranges from 17 mV/dec for the TFET without strain, down to 11 mV/dec for the device with strain whose Ge mole fraction up to 0.6, and average subthreshold swing ranges from 63 mV/dec down to 46 mV/dec.

The threshold voltage is one of the most important electrical parameters of a solid-state switch. For TFETs, the physical definition of threshold voltage is the gate voltage marking the transition between an exponential dependence and a linear dependence, of drain current on applied bias [12]. Figure 5 shows the threshold voltage of FD-SSOI TFET versus strain (equivalent Ge mole fraction in the relaxed SiGe buffer layer). The threshold voltage is extracted from Atlas simulations using transconductance change (TC) method, which universally defines the threshold voltage of any nonlinear device as the gate voltage corresponding to the maximum of the transconductance derivative [13]. It is shown that the threshold voltage decreases almost linearly with Ge mole fraction (from 1.25 V for no strain to 1.09 V for Ge mole fraction ).

#### 3. Model Derivation

##### 3.1. Length of the Depletion Regions

Now we calculate the lengths of two depletion regions ( and ). Since the basic structure of the FD-SSOI TFET is a gated PIN diode, the potential in the channel is modulated by the gate-source and drain-source voltage. To consider the influence of these two voltages on each other, and can be calculated by imposing and , but the calculation would be complicated. Here a useful approximation is made, separately considering the source-body junction and body-drain junction. In a junction, from the potential drop across the junction the length of the depletion region can be calculated [14]. Therefore, the values of and can be calculated aswithwhere is the boundary value of the potential at source depletion end, is the boundary value of the potential at drain depletion end, is the potential in intrinsic region due to the gate without influence of the junctions, is the intrinsic carrier concentration in strained Si [15], and is the strained Si dielectric constant.

##### 3.2. Surface Potential Model

For the FD-SSOI N-TFET structure in Figure 1, the 2D Poisson equation in the strained silicon layer can be written aswhere is the electrostatic potential in regions I, II, and III and is the strained Si layer effective doping and is equal to in the region I, in the region III, and in the region II.

The potential profile in the vertical direction in strained Si layer can be approximated by a parabolic function as [16]where the coefficients and are functions of only and is the surface potential in regions I, II, and III.

For region II, the coefficients and can be solved by the following boundary conditions:where is the dielectric constant of the gate dielectric, is the gate dielectric thickness, , and is the flatband voltage, which can be expressed as , with : where is the gate work function, is the Si work function, and are the increase in electron affinity and the decrease in the band gap of Si due to strain, respectively, is the thermal voltage, and are the density of states in the valence band in Si and strained Si, respectively, and are the hole density of states effective masses in Si and strained Si, respectively, and is the Ge mole fraction in substrate.

Substituting the coefficients and in (4) and then in (3), we obtain where , .

In the above relations, .

The above equation (7) is a simple second-order nonhomogenous differential equation which has a solution of the form

The electric field distribution can be written as

On the regions I and III, the fringing field effect is taken into account by conformal mapping techniques as ( must satisfy the condition ) [16]. Then, the surface potential in regions I and III can be written as

The electric field distribution in these regions can be written aswhere , , and .

Using the boundary conditions (12), the unknown functions , , , , , and in (8) and (10) can be obtained:

##### 3.3. Threshold Voltage Model

The physically based definition of threshold voltage for TFETs is the gate voltage marking the transition of drain current on applied bias between an exponential dependence and a linear dependence. This also marks the transition between the strong control and weak control of the tunneling energy barrier width at the tunnel junction by the gate voltage. The inflection point in tunneling energy barrier width () [3, 12] shows this transition point. The threshold voltage of FD-SSOI TFET is taken to be that value of gate-source voltage for which the potential in the point reaches the value . Hence, by substituting and into (8), we can get the following equation:In the above relation, , , and are the function of .

Threshold voltage values of FD-SSOI TFET can be determined by solving this equation numerically for , which are shown in Section 4.

#### 4. Model Evaluation

The threshold voltage is extracted from simulations using the TC method. This method locates the voltage where there is a transition between strong and weak control of the tunneling energy barrier width, consistent with the model formulation.

Figure 6 plots the variation of threshold voltage with change in strain (i.e., equivalent Ge mole fraction ). The line represents the model results, and scatter represents the simulation results. It can be found that the threshold voltage obtained from the model tracks the simulation values very well. We also observe that threshold voltage is lower for higher strain in the strain silicon layer. This reduction in the threshold voltage of FD-SSOI TFET with an increasing Ge mole fraction can be attributed to a reduced band gap at the tunnel junction. The model presented in this paper can describe this effect well.

The variation of threshold voltage with the gate length for and is plotted in Figure 7. As can be seen from Figure 7, there is no obvious change in threshold voltage with change in gate length. It is also observed that the threshold voltage of FD-SSOI TFETs is lower for higher strain. The threshold voltage values from our model are in close proximity with the simulation results. This suggests that scaling the gate length of FD-SSOI TFET has little effect on the threshold voltage as long as gate length is longer than some critical length at which too much P-I-N leakage current occurs in the off-state. In general, the critical length is about the order of 10 nm [17, 18], which is a function of , , , , and so forth and needs further study. Here, FD-SSOI TFET scaling is restricted to 20 nm.

In Figure 8, the variation of threshold voltage with change in strained Si layer thickness is plotted for and . It is observed that threshold voltage increases with increase in strained Si layer thickness.

Improved characteristics of FD-SSOI TFET can be obtained by careful choice of a gate dielectric. Figure 9 shows the variation of EOT (equivalent oxide thickness) with gate dielectric permittivity for = 3 nm. As shown in the figure, for a given gate dielectric thickness, the EOT decreases with increasing gate dielectric permittivity. Figure 10 shows the variation of threshold voltage with gate dielectric permittivity for different values of drain-source voltage and for a Ge mole fraction of 0.3. It is observed that the device with the high-*κ* gate dielectric or the thinner EOT has the low threshold voltage. A higher gate dielectric permittivity or a smaller EOT increases the gate control, thereby decreasing the threshold voltage. We can also observe that the threshold voltage is lower for lower drain-source voltage. This result can be confirmed from Figure 10. The proposed model can predict the change in threshold voltages induced by the high-*κ* gate dielectric very well.

#### 5. Conclusion

We have proposed and exhaustively simulated a novel nanoscale FD-SSOI TFET structure. Due to using SSOI structure, the FD-SSOI TFET shows high on-current and steeper SS, exhibiting significant performance improvement compared with traditional Si TFET. Furthermore, based on the physical definition of threshold voltage for FD-SSOI TFET, a threshold voltage model for FD-SSOI TFET has been developed. We have shown that the model can predict the trends of the device characteristics very well. The model can also predict the improved performance on the physical threshold voltage when using SSOI structure, high-*κ* dielectrics, and thin strained Si film and the limited effect on threshold voltage when scaling the gate length.

#### Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

#### Acknowledgment

The project is supported by the National Natural Science Foundation of China (Grant no. 61474085).

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#### Copyright

Copyright © 2015 Yu-Chen Li et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.