Table of Contents
Advances in Electronics
Volume 2015 (2015), Article ID 202131, 10 pages
Research Article

Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits

1Department of ECE, Mewar University, Rajasthan 312901, India
2Department of ECE, BVCOE, Paschim Vihar, New Delhi 110063, India
3SoE, CDAC Noida, Ministry of Communications and IT, Government of India, Noida, Uttar Pradesh 201307, India

Received 30 September 2014; Revised 25 December 2014; Accepted 25 December 2014

Academic Editor: Meiyong Liao

Copyright © 2015 Manoj Sharma and Arti Noor. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Previously, authors have proposed CPLAG and MCPLAG circuits extracting benefits of CPL family implemented based upon semiadiabatic logic for low power VLSI circuit design along with gating concept. Also authors have communicated RCPLAG circuits adding another dimension of reconfigurability into CPLAG/MCPLAG circuits. Moving ahead, in this paper, authors have implemented/reconfigured RCPLAG universal Nand/And gate and universal Nor/Or gate for extracting behavior of dynamic positive edge triggered DFF. Authors have also implemented Adder/Subtractor circuit using different techniques. Authors have also reported modification in PFAL semiadiabatic circuit family to further reduce the power dissipation. Functionality of these is verified and found to be satisfactory. Further these are examined rigorously with voltage, , temperature, and transistor size variation. Performance of these is examined with these variations with power dissipation, delays, rise, and fall times associated. From the analysis it is found that best operating condition for DFF based upon RCPLAG universal gate can be achieved at supply voltage lower than 3 V which can be used for different transistor size up to 36 μm. Average power dissipation is 0.2 μW at 1 V and 30 μW at 2 V at 100 ff 25°C approximately. Average power dissipated by CPLAG Adder/Subtractot is 58 μW. Modified PFAL circuit reduces average power by 9% approximately.