Reconfigurable CPLAG and Modified PFAL Adiabatic  Logic Circuits

<div>Avg. input power required for <svg height="12.4257pt" id="M26" style="vertical-align:-3.427751pt" version="1.1" viewbox="-0.0498162 -8.99795 13.1605 12.4257" width="13.1605pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><path d="M697 650H468L461 623L492 619C539 613 547 605 518 546C481 471 367 264 278 116H276C239 278 197 500 186 567C180 604 185 613 226 619L252 623L260 650H24L17 623C78 617 92 613 108 533L216 -11H247C365 200 515 462 560 529C616 612 624 615 689 623L697 650Z" id="g113-87"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="709" vert-adv-y="709"></glyph.data></g><g transform="matrix(.0095,0,0,-0.0095,7.641,3.264)"><path d="M490 97L476 124C442 96 405 70 398 70C392 70 390 78 396 114C419 243 448 379 463 432L457 436C446 436 431 439 418 442C393 447 368 451 343 451C281 451 204 418 155 381C74 320 24 206 24 107C24 23 59 -12 88 -12C118 -12 155 5 191 34C236 70 290 122 328 177H330L312 84C296 0 311 -12 331 -12C355 -12 425 24 490 97ZM374 387C371 367 360 299 347 264C323 202 187 53 142 53C128 53 113 73 113 120C113 224 157 332 221 380C241 395 274 403 303 403C330 403 360 395 374 387Z" id="g50-98"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="514" vert-adv-y="514"></glyph.data></g></svg> for DFF @RCPLAG Nand.</div>

Advances in Electronics

Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits

Figure 14