Reconfigurable CPLAG and Modified PFAL Adiabatic  Logic Circuits

<div><svg height="14.5866pt" id="M41" style="vertical-align:-5.588651pt" version="1.1" viewbox="-0.0498162 -8.99795 24.1266 14.5866" width="24.1266pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><path d="M697 650H468L461 623L492 619C539 613 547 605 518 546C481 471 367 264 278 116H276C239 278 197 500 186 567C180 604 185 613 226 619L252 623L260 650H24L17 623C78 617 92 613 108 533L216 -11H247C365 200 515 462 560 529C616 612 624 615 689 623L697 650Z" id="g113-87"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="709" vert-adv-y="709"></glyph.data></g><g transform="matrix(.0095,0,0,-0.0095,7.641,3.264)"><path d="M169 380V459C122 440 66 423 24 416V392C86 384 90 382 90 317V-135C90 -201 81 -207 17 -213V-240H253V-213C176 -207 169 -201 169 -125V6C182 -1 208 -11 238 -12C368 12 487 109 487 260C487 358 421 449 310 449C298 449 279 444 261 433L169 380ZM169 346C196 367 237 389 269 389C341 389 403 329 403 221C403 109 347 37 263 37C228 37 191 53 169 76V346Z" id="g190-113"></path><glyph.data ascent="989" descent="-360" horiz-adv-x="524" vert-adv-y="524"></glyph.data></g><g transform="matrix(.0095,0,0,-0.0095,12.506,3.264)"><path d="M518 50L491 51C452 54 444 60 444 110V444C429 441 405 437 377 434C348 430 314 427 287 426V403L323 397C356 392 365 386 365 333V99C331 66 293 51 257 51C212 51 169 75 169 164V299C169 366 169 413 172 444C156 441 128 437 101 433C75 430 50 427 29 426V403L57 397C82 391 90 386 90 333V137C90 29 147 -12 214 -12C241 -12 262 -4 291 13S342 48 365 65V-6L371 -12C390 -7 415 1 441 8C468 15 496 21 518 24V50Z" id="g190-118"></path><glyph.data ascent="989" descent="-360" horiz-adv-x="531" vert-adv-y="531"></glyph.data></g><g transform="matrix(.0095,0,0,-0.0095,17.589,3.264)"><path d="M238 0V26C174 32 166 38 166 104V712C132 700 70 683 18 677V653C81 647 87 645 87 577V104C87 38 78 32 15 26V0H238Z" id="g190-109"></path><glyph.data ascent="989" descent="-360" horiz-adv-x="253" vert-adv-y="253"></glyph.data></g><g transform="matrix(.0095,0,0,-0.0095,19.96,3.264)"><path d="M319 325C317 349 306 409 297 431C277 440 250 449 209 449C117 449 57 389 57 319C57 243 122 209 182 182C232 159 261 135 261 91C261 48 227 21 190 21C130 21 85 79 68 145L41 140C41 104 51 36 58 22C75 7 121 -12 172 -12C252 -12 337 35 337 126C337 195 286 231 210 262C166 281 126 304 126 348C126 388 152 417 191 417C240 417 274 378 294 318L319 325Z" id="g190-116"></path><glyph.data ascent="989" descent="-360" horiz-adv-x="367" vert-adv-y="367"></glyph.data></g></svg> avg. power consumed with respect to temperature variation.</div>

Advances in Electronics

Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits

Figure 20