Research Article
Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits
Table 6
Power utilization for PFAL versus modified PFAL.
| | (W) | Modified PFAL inverter | PFAL inverter | % reduction | Total reduction |
| | Pavg_Vpuls | 1.58E − 11 | 6.60E − 10 | 9.76E + 01 | 9.80E + 01 | | Pavg_Vin | 4.59E − 11 | 4.57E − 11 | −4.44E − 01 | | Pavg_Vinb | 2.29E − 10 | 2.31E − 10 | 8.76E − 01 |
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